ml7029 Oki Semiconductor, ml7029 Datasheet
ml7029
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ml7029 Summary of contents
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... OKI Semiconductor ML7029 Multifunction ADPCM CODEC GENERAL DESCRIPTION The ML7029 is a single channel ADPCM CODEC IC which performs mutual transcoding between the analog voice band signal and 32 kbps ADPCM serial data. FEATURES • Single 3 V Power Supply Operation (V • ADPCM Algorithm: • Full-Duplex Transmit/Receive Operation • ...
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... BLOCK DIAGRAM A/D AIN– Conv. 20 kΩ GSX D/A VFRO Conv. 20 kΩ VREF SG CR2-B7 CR2- BPF/ TXON/ LPF OFF CR3- CR2-B3 RXON/ LPF OFF CR2- MCU I/F FEDL7029-03 ML7029 PCM PCMSO Compander PCMSI IS ADPCM IR PCMRO PCM PCMRI Expander BCLK SYNC 2/29 ...
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... PIN CONFIGURATION (TOP VIEW) GSX AIN– VFRO PDN 15 NC: No Connection 30-Pin Plastic SSOP FEDL7029-03 ML7029 BCLK 28 SYNC 27 PCMSO 26 PCMSI PCMRO 22 PCMRI MCK 19 DEN 18 EXCK 17 DIN 16 DOUT 3/29 ...
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... The reset width (a “L” level period) should be 200 ns or more. Be sure to reset the control registers by executing this power down to keep this pin to digital “0”level for 200 ns or longer after the power is turned on and V ). The V A exceeds 2 FEDL7029-03 ML7029 pin must be kept as close D 4/29 ...
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... This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure 1. BCLK Shift clock input for the PCM and ADPCM data. The frequency is set in the range 256 times the SYNC frequency. Refer to Figure 1. FEDL7029-03 ML7029 5/29 ...
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... CR3-B1. Synchronize this signal with BCLK signal. SYNC is used to indicate the MSB of the PCM data stream. Refer to Figure 1. SYNC BCLK PCMSO/PCMSI/ MSB PCMRO/PCMRI IS/IR MSB Figure 1 PCM and ADPCM Interface Basic Timing 125 µs (SYNC = 8 kHz) LSB LSB FEDL7029-03 ML7029 6/29 ...
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... High Impedance (a) Data Write Timing Diagram (b) Data Read Timing Diagram High Impedance (a) Data Write Timing Diagram (b) Data Read Timing Diagram FEDL7029-03 ML7029 7/29 ...
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... Control and Detect Data PDN — — ALL RESET RESET MUTE MUTE GAIN1 GAIN0 ON/OFF GAIN2 Side Tone — — GAIN0 FEDL7029-03 ML7029 R R/W — — — — R/W PAD R/W GAIN1 GAIN0 HPF HPF — R/W 8k/11k ON/OFF 8/29 ...
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... BCLK ↔ SYNC 100 (see Fig. 3-1) BCLK ↔ SYNC 0 (see Fig. 3-2) SYNC (see Fig. 3-1) 1BCLK SYNC (see Fig. 3-2) 1BCLK — 100 — 100 Digital Output Pins — 10+0.1 FEDL7029-03 ML7029 Rating Unit –.3 to +5 °C –55 to +150 Typ. Max. Unit 3.0 +3.6 V ° ...
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... C GSX, VFRO L V GSX, VFRO ( kΩ GSX, VFRO SG↔AG 10+0.1µ (Rise time to max. 90% level) PP FEDL7029-03 ML7029 (V = 2 –25 to +70°C) DD Min. Typ. Max. Unit — 6 — 0.01 0.1 mA — — 2.0 µA — — 0.5 µA 2.4 — ...
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... Hz – 1015 Hz – 1015 Hz – 1015 Hz –40 AIN– — (*4) AIN– — (*4) 1015 Hz(GSX) SYNC = 8 kHz 1015 Hz(VFRO) SYNC = 8 kHz FEDL7029-03 ML7029 (V = 2 –25 to +70°C) DD Min. Typ. Max. Unit 30 — — dB –0.5 — 1 Reference dB – ...
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... Fig. 4 EXCK EXCK Symbol Condition All stages, to programmed value D G SYNC = 8 kHz FEDL7029-03 ML7029 (V = 2 –20 to +70°C) DD Min. Typ. Max. Unit 0 — 200 ns 0 — 200 ns 0 — 200 ns 0 — 200 ...
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... MSB PCMSO t SDX IS MSB t SDX Receive Side PCM/ADPCM Data Interface BCLK SYNC t RD1 MSB PCMRO SDR MSB IR Figure 3-1 PCM/ADPCM Data Interface (Continuous BCLK XD2 t XD3 LSB RD2 RD3 LSB FEDL7029-03 ML7029 t XD3 LSB t RD3 LSB 13/29 ...
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... WSB SYNC t XD1 MSB PCMSO IS MSB Receive Side PCM/ADPCM Data Interface BCLK WSB SYNC t t RD2 RD1 MSB PCMRO MSB Figure 3-2 PCM/ADPCM Data Interface (Burst Mode Clock) t XD2 t XD3 LSB t RD3 t DH LSB FEDL7029-03 ML7029 t XD3 LSB t RD3 LSB 14/29 ...
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... DOUT Figure 4-2 Serial Control Port Interface (DIN = 16 bits FEDL7029-03 ML7029 15/29 9 ...
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... B4 B3 PDN ALL — — 0/Power-on, 1/Power-down RESET RX RESET TX MUTE RX MUTE Data rates in parentheses: when SYNC = 8 kHz 1/ Reset* 1/Mute 1/Mute 1/inserted in the receive side voice path loss 0/no PAD FEDL7029-03 ML7029 — — — — RX PAD 16/29 ...
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... B2 B1 – – – FEDL7029-03 ML7029 GAIN2 RX GAIN1 RX GAIN0 Receive Gain 0 – – – 17/29 ...
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... For the frequency characteristics, refer to Figures the Reference Data Side Tone — — GAIN0 Side Tone Path Gain 0 0 OFF 0 1 – – – – – – –9 dB 0/ON, 1/OFF FEDL7029-03 ML7029 HPF HPF — 8k/11k ON/OFF * 0 0 18/29 ...
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... Power-down GSX AIN– ML7029 VFRO PDN 15 FEDL7029-03 ML7029 PCM I/F BCLK 29 SYNC 28 PCMSO 27 PCMSI 26 ADPCM DATA PCMRO 23 PCMRI Master Clock MCK 20 DEN 19 EXCK 18 MCU I/F DIN ...
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... MAX. (Number of clocks in burst mode)–1 µs 1/f sample PCM Data Input µ (Range of Data Slip Occurrence) A µ 0.83/f s sample Figure 6 µs 1/f sample ADPCM Data Input µ (Range of Data Slip Occurrence) µ s sample B Figure 7 FEDL7029-03 ML7029 20/29 ...
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... The data slip occurs at the timing of 1 and 2 above. Therefore, taking internal clock jitters and IC internal delay into consideration, the timing of SYNC and BCLK signals should not be set up in the range of about 1 µs from the timing A and B. Latch ADPCM COD A Internal Clock Generation ADPCM DEC Latch Figure 8 FEDL7029-03 ML7029 Latch P (2) Latch S/P IR 21/29 ...
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... Figure 9 Transmit Bandpass Filter Characteristic 10 0 -10 -20 -30 -40 -50 -60 -70 -80 100 Figure 10 Transmit Lowpass Filter Characteristic kHz Transmit BPF Characteristic 1000 Frequency (Hz) ( kHz, CR3-B1 (0, 0 8kHz Transmit LPF Characteristic 1000 Frequency (Hz) ( kHz, CR3-B1 (0, 1)) FEDL7029-03 ML7029 10000 10000 22/29 ...
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... Figure 11 Transmit Bandpass Filter Characteristic 10 0 -10 -20 -30 -40 -50 -60 -70 -80 100 Figure 12 Transmit Lowpass Filter Characteristic Fs = 11.025 kHz Transmit BPF Characteristic 1000 Frequency (Hz) (Fs = 11.025 kHz, CR3-B1 (1, 0 11.025 kHz Transmit LPF Characteristic 1000 Frequency (Hz) (Fs = 11.025 kHz, CR3-B1 (1, 1)) FEDL7029-03 ML7029 10000 10000 23/29 ...
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... Figure 13 Receive Lowpass Filter Characteristic 10 0 -10 -20 -30 -40 -50 -60 -70 -80 100 Figure 14 Receive Lowpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1 (1, *)) kHz Receive LPF Characteristic 1000 Frequency (Hz) ( kHz, CR3-B1 (0, *)) Fs = 11.025 kHz Receive LPF Characteristic 1000 Frequency (Hz) FEDL7029-03 ML7029 10000 10000 24/29 ...
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... IH V Digital input pin IL f MCK MCK1 f MCK –0.01% MCK2 f SYNC SYNC D — MCK SD19T1 — SD19T2 — SD19R1 — SD19R2 — FEDL7029-03 ML7029 Min. Typ. Max. Unit 3.0 — 3.6 V °C –25 — +50 — 0.05 × — 24.624 — ...
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... IH V Digital input pin IL f MCK MCK1 f MCK –0.01% MCK2 f SYNC SYNC D — MCK SD19T1 — SD19T2 — SD19R1 — SD19R2 — FEDL7029-03 ML7029 Min. Typ. Max. Unit 3.3 — 3.6 V °C –25 — +50 — 0.05 × — 27.216 — ...
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... FEDL7029-03 (Unit: mm) Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating (≥5µm) Package weight (g) 0.19 TYP. Rev. No./Last Revised 5/Dec. 5, 1996 ML7029 27/29 ...
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... OKI Semiconductor REVISION HISTORY Document No. Date FEDL7029-02 Nov. 2001 FEDL7029-03 Feb.18, 2004 Page Previous Current Edition Edition – – Final edition 2 – – Final edition 3 Changed “Symbol” of Setup Time and Hold 9 9 Time for PCM/ ADPCM. FEDL7029-03 ML7029 Description 28/29 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL7029-03 Copyright 2004 Oki Electric Industry Co., Ltd. ML7029 29/29 ...