ml7029 Oki Semiconductor, ml7029 Datasheet - Page 21

• Manufacturer Part Number: ml7029
• Description: Multifunction Adpcm Codec
• Manufacturer: Oki Semiconductor

(1): PCM data serial to parallel conversion output
(2): ADPCM data serial to parallel conversion output
A: (1) Data internal latch timing
B: (2) Data internal latch timing
In this device, internal operating timing is generated according to the SYNC signal (see Figure 8). Therefore, a
data slip may occur in the following timing when the PCM and ADPCM data is input.
1. When the PCM signal (PCMSI) is captured
2. When the ADPCM signal (IR) is captured
The data slip occurs at the timing of 1 and 2 above. Therefore, taking internal clock jitters and IC internal delay
into consideration, the timing of SYNC and BCLK signals should not be set up in the range of about 1 µs from
the timing A and B.
OKI Semiconductor
If TS: PCM signal output (1) after serial/parallel conversion and A: internal latch timing in Figure 6 overlap, a
data slip occurs.
If Tr: ADPCM signal output (2) after serial/parallel conversion and B: internal latch timing in Figure 7 overlap,
a data slip occurs.
PCMSI
SYNC
BCLK
PCMRO
S/P
P/S
(1)
Latch
Latch
A
Internal Clock Generation
Figure 8
ADPCM COD
ADPCM DEC
B
Latch
Latch
(2)
P/S
S/P
FEDL7029-03
IR
IS
ML7029
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