ml7074a-003 Oki Semiconductor, ml7074a-003 Datasheet - Page 23

• Manufacturer Part Number: ml7074a-003
• Description: Voip Codec
• Manufacturer: Oki Semiconductor

This is the input/output control input pin of SYNC and BCLK. The pin becomes input at “0” level and output at
This is the 8 kHz sync signal input/output pin of PCM signals. When CLKSEL is “0”, input continuously an 8 kHz
This is the shift clock input/output pin for the PCM signal. When CLKSEL is “0”, it is necessary to input to this pin
Note: The input/output control and frequencies of the above SYNC and BLCK signals will be as shown in Table 1
This is the PCM signal output pin for the transmitting section. The PCM signal is output in synchronization with
This is the PCM signal input pin for the receiving section. The data is entered starting from the MSB by shift on the
The basic timing chart of the PCM I/F mode is shown in Fig. 11.
Fix input with “0” or “1” when the mutual conversion function is not used (CR11-B0 = “0”) or when the PCM I/F
“1” level.
clock synchronous with BCLK. Further, when CLKSEL is “1”, this pin outputs an 8 kHz clock synchronous with
BCLK.
synchronization is used when it is “1”.
a clock signal that is synchronous with SYNC. Input a 64 to 2048 kHz clock when the G.711 mode or the G.726
mode has been selected, and input a 128 to 2048 kHz clock when the 16-bit linear mode has been selected. When
CLKSEL is “1”, this pin outputs a clock that is synchronous with SYNC. This pin outputs a 64 kHz clock when the
G.711 mode or the G.726 mode has been selected, and outputs an 128 kHz clock when the 16-bit linear mode or
G.729.A mode has been selected.
the rising edges of SYNC and BCLK. The PCMO outputs the data only during the valid data segment in the
selected coding format and goes to the high impedance state during all other segments. The basic timing chart of
the PCM I/F mode is shown in Fig. 11. The PCMO output will be in the high impedance state when the mutual
conversion function is not used (CR11-B0 = “0”) or when the PCM I/F mode is not used (CR12-B0 = “0”).
falling edge of BCLK.
mode (CR12-B0 = “0”) is not used.
CLKSEL
SYNC
BCLK
PCMO
PCMI
OKI Semiconductor
below.
CLKSEL
Long frame synchronization is used when CR0-B1 (LONG/SHORT) is “0” and short frame
“0”
“1”
(8 kHz)
(8 kHz)
Output
SYNC
Input
Table 1 Input/output control of SYNC and BCLK
(64 kHz to 2048 kHz)
(64 kHz or 128 kHz)
Output
BCLK
Input
Input a continuous clock after starting the power
supply.
Input a 64 to 2048 kHz clock when G.711 or G.726 is
selected.
Input a 128 to 2048 kHz clock when 16-bit linear
mode is selected.
An “L” level is output during the power down mode.
A 64 kHz clock is output when G.711 or G.726 is
selected.
A 128 kHz clock is output when G.729.A or 16-bit
linear mode is selected.
Remarks
FEDL7074-003FULL-01
ML7074-003 GA
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