mt8885an1 Zarlink Semiconductor, mt8885an1 Datasheet - Page 15

• Manufacturer Part Number: mt8885an1
• Description: Integrated Dtmf Transceiver With Power-down And Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

Note 1:
Bit
b0
b1
b2
b3
Bit
b0
b1
b2
b3
When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down.
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
RECEIVE DATA REGISTER
FULL
DELAYED STEERING
BURST
Name
RxEN
S/D
C/R
Name
IRQ
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written to
the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power-down mode. See
Note 1 below.
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7 - Control Register B Description
Table 8 - Status Register Description
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
and transmitter is ready for new
data.
Valid data is in the Receive Data
Register.
Set upon the valid detection of the
absence of a DTMF signal.
Pause duration has terminated
Zarlink Semiconductor Inc.
Status Flag Set
MT8885
15
Description
Interrupt is inactive. Cleared after
Status Register is read.
Cleared after Status Register is
read or when in non-burst mode.
Cleared after Status Register is
read.
Cleared upon the detection of a
valid DTMF signal.
Status Flag Cleared
Data Sheet