mt89l86apr1 Zarlink Semiconductor, mt89l86apr1 Datasheet - Page 4

• Manufacturer Part Number: mt89l86apr1
• Description: 512 X 256 Channels 3.3 V Multiple Rate Digital Switch Mrdx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
PLCC
37-39
41-43
44
35
36
18
28
44
6
1
Pin #
SSOP
40-42
44-46
48
38
39
19
30
47
48
6
STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin is
STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of this pin is
AS/ALE
STo5-0
STi15/
Name
CSTo
ODE
STo9
IM
determined by the switching configuration enabled. If non-multiplexed CPU bus is used along
with data rates employing 8.192 Mb/s rates, this pin provides A7 address input function. For
2.048 Mb/s applications or when the multiplexed CPU bus interface is selected, this pin
assumes STo7 function. See Tables 1, 2, 6 & 7 for more details.
Note that for applications where A7 input and STo7 output are required simultaneously (e.g.,
8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin STi7/A7.
determined by the switching configuration enabled. If non-multiplexed CPU bus is used along
with a higher data rate employing 8.192 or 4.096 Mb/s, this pin provides the A6 address input
function. For 2.048 Mb/s applications or when the multiplexed CPU bus interface is selected,
this pin assumes STo6 function. See Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 input and STo6 output are required simultaneously
(e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion applications), the A6 input
should be connected to pin STi6/A6.
ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams. These serial
streams may be composed of 32, 64 and 128 channels at data rates of 2.048, 4.096 or 8.192
Mbit/s, respectively.
Output Drive Enable (5 V tolerant Input). This is the output enable input for the STo0 to
STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is high each
channel may still be set to high impedance by using per-channel control bits in Connect
Memory High.
Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256 bits per frame.
The level of each bit is determined by the CSTo bit in the Connect Memory high locations.
Address Strobe or Latch Enable (5 V tolerant Input). This input is only used if multiplexed
bus is selected via the IM input pin.
The falling edge of this signal is used to sample the address into the address latch circuit. When
the non-multiplexed bus interface is selected, this input is not required and should be connected
to ground.
CPU Interface Mode (5 V tolerant Input). If HIGH, this input configures the MT89L86 in the
multiplexed microprocessor bus mode. When this input pin is connected to ground, the
MT89L86 assumes non-multiplexed CPU interface.
ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only used if
multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is enabled in
the SCB bits (IMS register), this pin is an input receiving serial ST-BUS stream 15 at a data rate
of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration section), this pin is
the ST-BUS stream 9 output.
When non-multiplexed bus structure is used, this pin should be connected to ground.
Zarlink Semiconductor Inc.
MT89L86
4
Description
Data Sheet