mt89l86apr1 Zarlink Semiconductor, mt89l86apr1 Datasheet - Page 8

• Manufacturer Part Number: mt89l86apr1
• Description: 512 X 256 Channels 3.3 V Multiple Rate Digital Switch Mrdx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

MT89L86
Data Sheet
along with the permanently connected STi0/STo0 and STi1/STo1 streams. The two additional pair of streams called
stream pair A and stream pair B, should be selected in the Stream Pair Selection register (SPS). The device clock
for this operation is 4.096 MHz compatible to ST-BUS and GCI interfaces. In addition, the per-channel selection
between variable or constant throughput delay is available.
In the nibble switching configuration, 4-bit wide 32 Kb/s data channels can be switched within the device. Every
serial stream is run at 2.048 Mb/s and transports 64 nibbles per frame. When the Nibble Switching is selected at
SCB bits, the 3.3V MT89L86 automatically assumes a 8-input x 4-output stream configuration, providing a blocking
switch matrix of 512 x 256 nibbles. If a non-blocking switch matrix is required for nibble switching, the switch
capacity is reduced to 256 x 256 channel with a 4 input x 4 output configuration; the non-blocking matrix can be
arranged by the user by selecting any four of the 8 input streams. In nibble switching the interface clock is
4.096 MHz.
Serial Links with Data Rates at 4.096 Mb/s
Two I/O configurations can be enabled by the SCB bits when input and output data rates are 4.096 Mb/s on each
serial stream: 8 x 4 and 4 x 4. When 8 x 4 switching configuration is selected, a 512 x 256 channel blocking switch
is available with serial streams carrying 64, 64 Kb/s channels each. For this operation, a 4.096 MHz interface clock
equal to the bit rate should be provided to the 3.3 V MT89L86. Only variable throughput delay mode is provided.
In the 4 x 4 switching configuration, a 256 x 256 channel non-blocking switch is available with serial streams
carrying 64, 64 Kb/s channels each. In this configuration, the interface clock is 4.096 MHz and the per-channel
selection between variable and constant throughput delay operation is provided. Figure 19 shows the timing for
4.096 Mb/s operation.
Serial Links with Data Rates at 8.192 Mb/s
Only 2 input x 2 output stream configuration is available for 8.192 Mb/s, allowing a 256 x 256 channel non-blocking
switch matrix to be implemented. To enable this operation, the IDR bits should be programmed to select 8.192 Mb/s
rates and the SCB bits have no effect. At 8.192 Mb/s, every input and output stream provides 128 time-slots per
frame. The interface clock for this operation should be 8.192 MHz. Figure 19 shows the timing for 8.192 Mb/s
operation.
Table 1 summarizes the 3.3 V MT89L86 switching configurations for identical I/O data rates.
8
Zarlink Semiconductor Inc.