zl30109 Zarlink Semiconductor, zl30109 Datasheet - Page 9

• Manufacturer Part Number: zl30109
• Description: Ds1/e1 System Synchronizer With 19.44 Mhz Output
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
39
40
41
42
43
44
45
46
47
48
49
50
51
52
C4/C65o
C8/C32o
F8/F32o
F4/F65o
AGND
AGND
AGND
Name
AV
AV
C19o
C16o
F16o
C2o
IC
DD
DD
Clock 19.44 MHz (Output). This output is used in SONET/SDH applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Analog Ground. 0 V
Analog Ground. 0 V
Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at
2.048 Mbps, 4.096 Mbps or 65.536 MHz (ST-BUS 65.536 Mbps). The output frequency is
selected via the OUT_SEL pin.
Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI
operation at 8.192 Mbps or for operation with a 32.768 MHz clock. The output frequency
is selected via the OUT_SEL pin.
Positive Analog Supply Voltage. +3.3 V
Positive Analog Supply Voltage. +3.3 V
Clock 2.048 MHz (Output). This output is used for standard E1 interface timing and for
ST-BUS operation at 2.048 Mbps.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Clock 16.384 MHz (Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse (OUT_SEL=0)
or it is an 8 kHz 31 ns active high framing pulse (OUT_SEL=1), which marks the
beginning of a frame.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Frame Pulse ST-BUS 2.048 Mbps or ST-BUS at 65.536 MHz clock (Output). This
output is an 8 kHz 244 ns active low framing pulse (OUT_SEL=0), which marks the
beginning of an ST-BUS frame. This is typically used for ST-BUS operation at
2.048 Mbps and 4.096 Mbps. Or this output is an 8 kHz 15 ns active low framing pulse
(OUT_SEL=1), typically used for ST-BUS operation with a clock rate of 65.536 MHz.
Frame Pulse ST-BUS 8.192 Mbps (Output). This is an 8 kHz 61 ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mbps.
Analog Ground. 0 V
Internal Connection. Connect this pin to ground.
Zarlink Semiconductor Inc.
ZL30109
9
Description
DC
DC
nominal.
nominal.
Data Sheet