ttsv02622 ETC-unknow, ttsv02622 Datasheet - Page 28

• Manufacturer Part Number: ttsv02622
• Description: Sts-24 Backplane Transceiver
• Manufacturer: ETC-unknow

TTSV02622 STS-24 Backplane Transceiver
Receiver Block
FIFO Subblock (Backplane to Line)
The FIFO subblock consists of a 24 by 10-bit FIFO per STS-12. This FIFO will be used to align up to ±154.3 ns of
interlink skew and to transfer to the system clock.
This FIFO sync block takes metastable hardened frame pulses from the write control blocks and produces sync
signals that indicate when the read control blocks should begin reading from the first FIFO location. On top of the
sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart
for alignment (i.e., greater than 18 clocks apart). Sync and error signals are sent to read control block for align-
ment.
The read control block is synchronized only once on start-up, and any further synchronizing is software (S/W) con-
trolled. The action of resynchronizing a read control block will always cause a data hit. A software register allows
the read control block to be resynchronized.
Recommended Procedure for Synchronization of Selected Streams
Pointer Mover Subblock (Backplane to Line)
The pointer mover simply maps incoming frames to the line framing. The K1/K2 bytes and H1—SS bits are also
passed through to the pointer generator so that the line can receive them. The mover will handle both concatena-
tions inside the STS-12, and to other STS-12s inside the TTSV02622.
Pointer Interpreter State Machine
The pointer interpreter is minimized as much as possible to keep the gate count low. In keeping with that goal, the
pointer interpreter has only three states (NORM, AIS, and CONC). The interpreter’s highest priority is to maintain
accurate dataflow (i.e., valid SPE only). This will ensure that any errors in the pointer value will be corrected by a
standard pointer interpreter without any data hits. This means that error checking for increment, decrement, and
NDF (i.e., 8 of 10) are maintained in order to ensure accurate dataflow. A single valid pointer (i.e., 0—782) that dif-
fers from the current pointer will be ignored. Two consecutive incoming valid pointers that differ from the current
pointer will cause a reset of the J1 location to the latest pointer value (the generator will then produce an NDF).
This block is designed to handle single bit errors without affecting dataflow or changing state, but it is not compliant
with SONET standards.
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FIFO Sync Subblock (Backplane to Line)
Force AIS-L in all streams to be synchronized.
Wait four frames.
Write a 1 to the FIFO alignment resynchronizing register, bit DB1 of register 0x06.
Wait four frames.
Release the AIS-L in all streams.
(continued)
Agere Systems Inc.
June 2003