zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 42

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

1.7.8 VOICE
A voice function includes the following:
The data generated through an external ADC is input to the voice block in the ZIC2410 via an
I2S interface. Data received via I2S is compressed at the voice codec, and stored in the Voice
TXFIFO. The data is then transferred to the MAC TX FIFO through DMA operation and finally
transmitted through the PHY layer.
By contrast, received data in the MAC RX FIFO is transferred to the Voice RXFIFO and
decompressed in the voice codec. It is finally transferred to an external DAC via I2S interface.
I2S is commonly used for transferring/receiving voice data. Voice data can be transferred or
received via SPI or UART interface as well.
Voice codec supports u-law, a-law and ADPCM methods.
If the voice codec function is not needed, it can be bypassed.
In I2S interface, data is transferred MSB first from the left channel, and then from the right
channel. There are two ways to send data via I2S TX: writing data to the register either by
software, or by hardware. This is enabled by using the POP field in STXMODE (0x252d).
Similarly, there are two ways to receive data via I2S RX: the first is reading the register by
software, and the other is by the PUSH field in SRXMODE (0x253d)
There are four modes in I2S interface as follows.
In I2S mode, left channel data is transferred in order. When left channel data is transferred,
LRCK value is ‘0’ and when right channel data is transferred, LRCK value is 0. Transferred data
and LECK is changed at the falling edge. Refer to Figure 22 (a) below.
In Left Justified mode, left channel data is transferred whenever LRCK=1 and right channel data
is transferred, whenever LRCK =0. LRCK is changed at the falling edge of BLCK and
Transferred data is changed at the rising edge of BCLK. Refer to Figure 23 (b) below.
In Right Justified mode, left channel data allows last LSB to be output before LRCK value goes
to ‘0’ and right channel data allows last LSB to be output before LRCK value goes to ‘1’.
LRCK value is changed at the falling edge of BCLK. Output data is changed at the rising edge
of BCLK. Refer to Figure 24 (c) below.
In DSP mode, after LRCK outputs to ‘1’ for one period of BCLK, it goes to ‘0’. After that, left
channel data is outputted and then right channel data is outputted. LRCK value is changed at
the falling edge of BCLK. Output data is changed at the rising edge of BCLK. Refer to Figure
25 (d) below.
Figure 22, Figure 23, Figure 24, and Figure 25 show the interface method for each mode and
I2S TX block is selected as Master. The setting of register is as follows. MS field in STXAIC
Rev A
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•
•
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I2S Interface
Voice CODEC (u-law / a-law / ADPCM)
Voice FIFO
DMA
I2S mode
Left Justified mode
Right Justified mode
DSP mode
1.7.8.1 I2S
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
1.7.8.1
1.7.8.2
1.7.8.3
1.7.8.3
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