hi-3200 Holt Integrated Circuits, Inc., hi-3200 Datasheet
hi-3200
Related parts for hi-3200
hi-3200 Summary of contents
Page 1
... The HI-3200 interfaces directly with Holt’s HI-8448 octal ARINC 429 receiver IC, HI-8596 or HI-8592 ARINC 429 line drivers and HI-3110 integrated CAN controller / transceiver. The HI-3201 is identical to the HI-3200 except it comes in an 80-pin PQFP package with eight instead of two ARINC 429 bit monitor pins. APPLICATION ...
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... CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 ARINC 429 TRANSMITTER 0 TRANSMIT SCHEDULER 0 TRANSMIT TIMER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 HI-3200, HI-3201 Host CPU ARINC 429 SPI Interrupt Handler ARINC 429 RECEIVE DATA MEMORY ARINC 825 (CAN) Descriptor Table FILTER TABLE FIFO ...
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... APPLICATION OVERVIEW The HI-3200 is a flexible device for managing ARINC 429 and ARINC 825 communications and data storage in many avionics applications. The device architecture centers around a 32K x 8 static RAM used for data storage, data filtering tables and table-driven transmission schedulers. Once configured, the device ...
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... Example 4. ARINC 429 Data transmission using on-chip schedulers HCSB HSCLK Host CPU SPI HMOSI HMISO ECSB ESCLK EEPROM Auto-Initialization EMOSI SPI EEPROM EMISO HI-3200, HI-3201 FILTER TABLE FIFO LABEL RECEIVER 0 FILTER FIFO STATUS FIFO EMPTY FIFO THRESHOLD FIFO FULL TRANSMITTER 0 TRANSMITTER 1 SPI TRANSMITTER 2 ...
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... Example 6. ARINC 825 (CAN) bus Monitor / Receiver CCSB CSCLK CMOSI CMISO CMROUT COSC CGP2 Configuration HI-3110 & Control CSTAT Transceiver HI-3200 HI-3200, HI-3201 Channel 7, Label FF “ “ “ Channel 7, Label 01 Channel 7, Label 00 Descriptor Table 3 Channel 6, Label FF “ “ “ Channel 6, Label 01 Channel 6, Label 00 Channel 5, Label FF “ ...
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... Example 7. ARINC 825 (CAN) Terminal / Data Manager HCSB HSCLK HMOSI HMISO Host CPU MINT ARINC 825 / CAN INTERRUPT MINTACK CONTROL HI-3200, HI-3201 ARINC 825 / CAN TRANSMITTER ARINC 825 / CAN FILTER / MASK TABLE ARINC825 / CAN RECEIVE DATA ARINC825 / CAN MEMORY FILTER ...
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... TRANSMIT TRANSMITTER 2 SCHEDULER 2 TRANSMIT TIMER ARINC 429 TRANSMITTER 1 TRANSMIT SCHEDULER 1 TRANSMIT TIMER ARINC 429 TRANSMITTER 0 TRANSMIT SCHEDULER 0 TRANSMIT TIMER HI-3200, HI-3201 Channel 7, Label FF “ “ “ Channel 7, Label 01 Channel 7, Label 00 Channel 6, Label FF “ “ “ Channel 6, Label 01 Channel 6, Label 00 Channel 5, Label FF “ ...
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... MODE2 through MODE0 define HI-3200 start-up and initialization mode Master Reset to HI-3200 Active High Multiplexed with MODE0 pin, PROG initiates HI-3200 Auto-Initialization EEPROM programming routine READY goes high when post-RESET initialization is complete Master enable signal for ARINC 429 and CAN transmit schedulers ...
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... HI-3200 MEMORY MAP 0x8XXX Configuration Registers 0x8000 0x7FFF CAN TX ID Look-Up Table 0x7C00 0x7BFF Look-up Tables 0x79C0 0x79BF Transmit Schedule 0x6000 0x5FFF ARINC 429 TX3 Transmit Schedule 0x5800 0x57FF ARINC 429 TX2 Transmit Schedule 0x5000 0x4FFF ARINC 429 TX1 Transmit Schedule ...
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... Indicates Interrupt type CIAR CAN bus Interrupt vector AMFF ARINC 429 Multiplexed FIFO flags ATRB ARINC 429 Transmitter Ready flags MSR Indicates HI-3200 current status MCR HI-3200 global configuration ARXC0 Configures ARINC 429 receive channel 0 ARXC1 Configures ARINC 429 receive channel 1 ARXC2 ...
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... PIN ARXBIT7 CONFIG REG 2 0x8070 R BIST CONTROL/STATUS 0x8071 R BIST FAIL ADDRESS [7:0] 0x8072 R BIST FAIL ADDRESS [12:8] 0x8073 R AUTO-INIT FAIL LS ADDRESS [7:0] 0x8074 R AUTO-INIT FAIL MS ADDRESS [15:8] HI-3200, HI-3201 MNEMONIC ARXBIT ARX0CR1 ARX0CR2 ARX1CR1 ARX1CR2 ARX2CR1 ARX2CR2 ARX3CR1 ARX3CR2 ARX4CR1 ARX4CR2 ARX5CR1 ARX5CR2 ARX6CR1 ARX6CR2 ...
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... A429TX R/W 0 This bit must be set to a “1” to allow the HI-3200 to transmit ARINC 429 data on any of the four channels. If set to a zero, the HI-3200 will not output ARINC 429 data and the ARINC 429 transmit sequencers will remain in their reset state. ...
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... HI-3200, HI-3201 The HI-3110 OSCIN clock frequency must be set to achieve the desired bit rate. The HI-3200 COSC output signal provides a convenient 24MHz clock source for the HI-3110. For a full description of CAN Bus timing requirements, please refer to the Holt HI-3110 data sheet. ...
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... TSeg1 should be a minimum of 5Tq for Phase Seg2 (TSeg2) = 2Tq and SJW = 1Tq. TSEG2 bits <2:0> etc. HI-3200 Operational Status Information The Master Status Register may be read at any time to determine the current operational state of the HI-3200: MASTER STATUS REGISTER (Address 0x800E) Bit Name ...
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... ARINC 429 RECEIVE OPERATION The HI-3200 can receive ARINC 429 messages from up to eight ARINC 429 receive buses. External analog line receivers handle the physical layer connection ARINC 429 Receive Channel Configuration Each of the eight possible ARINC 429 Receive channels is configured using its own Control Register. Register address 0x8010 controls ARINC 429 Receive channel #0, register address 0x8011 controls channel #1 and so on ...
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... The eight ARINC 429 RX Control Registers, ARXC0 - 7, define the characteristics of each receive channel. The ARINC 429 receive function of the HI-3200 is acti- vated by setting the A429RX bit in the Master Control Register. When an ARINC 429 message is received by the HI-3200 on any bus checked for protocol compliance ...
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... Transmit scheduler #1 reads any bytes from the block. 0 NEW TX0 R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block reset when the ARINC 429 Transmit scheduler #0 reads any bytes from the block. HI-3200, HI-3201 Label = 0xFF Label = 0x0F 7 Label = 0x07 ...
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... ARINC 429 received message Messages (32-bits) HI-3200, HI-3201 The FIFOs are empty following Reset. All three status registers are cleared. When an ARINC 429 message is written to a FIFO, its FIFO NOT EMPTY bit is set to a “1”. When the FIFO contains more than the user-defined ...
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... This bit is set to “1” if FIFO #2 contains 32 ARINC 429 messages 1 AFFF 1 R/W 0 This bit is set to “1” if FIFO #1 contains 32 ARINC 429 messages 0 AFFF 0 R/W 0 This bit is set to “1” if FIFO #0 contains 32 ARINC 429 messages HI-3200, HI-3201 LSB MSB 7 6 ...
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... LSB MSB When in loop-back mode, incoming ARINC 429 messages are ignored by the HI-3200. When running in loop-back mode the ARINC 429 transmit pins may be disabled by pulling the TXMSK input high. This prevents test messages from being output to the external ARINC 429 transmit buses ...
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... Conversely, the data field MSB is bit 31. So the bit significance of the label byte and data fields are opposite. The HI-3200 may be programmed to “flip” the bit ordering of the label byte as soon received and immediately prior to transmission. This is accomplished by setting the AFLIP bit to a “ ...
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... Functionality is exactly the same. The register addresses for each pin specification are listed in the Register Map section (see page 11). Note that HI-3200 provides external monitoring of two bits through pins ARXBIT1 and ARXBIT0, whereas the HI-3201 provides external monitoring of eight bits through pins ARXBIT7 to ARXBIT0. ...
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... CAN BUS RECEIVE OPERATION The HI-3200 can receive CAN frames from a single CAN bus using an external HI-3110 IC to handle the CAN bus protocol and physical layer connection CAN Received Data Management The HI-3200 interfaces to a CAN bus using an external HI- 3110 CAN Controller / Transceiver IC. Communication between the HI-3200 and HI-3110 is handled by a dedicated high speed serial SPI link ...
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... CAN Received Data Filter, Filter Mask and Data Storage Organization CAN FILTER / MAP TABLE (3072 x 8) CAN CAN RECEIVE FILTER DATA RAM ( HI-3200, HI-3201 Filter 0xFF Filter 0x0F 7 6 Filter 0x07 Mask 255 0x3FFF Acceptance Filter 255 0x3FF4 Mask 2 0x341E ...
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... ARINC 429 Transmit scheduler #1 reads any bytes from the block. 0 NEW TX0 R/W 0 This bit is set when a new CAN frame is received and stored in this block reset when the ARINC 429 Transmit scheduler #0 reads any bytes from the block. HI-3200, HI-3201 ...
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... ARINC 429 TRANSMIT OPERATION The HI-3200 has four on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers such as the Holt HI-8570. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction generated automatically using the four ARINC 429 message schedulers. ...
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... CPU populated fixed values, or values from specific locations within the ARINC 429 receive memory or CAN bus receive memory. Action HI-3200, HI-3201 The user is responsible for construction of the descriptor table and for setting the Repetition Rate prior to asserting RUN/STOP ...
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... Control Register SKIP bit is a zero. If the SKIP bit is a one, the sequencer will wait until the next rollover of the Repetition Rate Counter before starting a new cycle. HI-3200, HI-3201 Current Sequence number ...
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... XXXXXXXX 010 XXXXX LLLLLLLL 011 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 XBBBB NNNNNNNN 111 XBBBB NNNNNNNN HI-3200, HI-3201 Op-Code Index LSB MSB MSB ACTION BYTE VALUE BYTE Description End of sequence. When op-code 000 is encountered by the sequencer ...
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... XXXXX LLLLLLLL 011 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 XBBBB NNNNNNNN 111 XBBBB NNNNNNNN HI-3200, HI-3201 Op-Code Index LSB MSB MSB ACTION BYTE Description No-Op op-code. ARINC 429 word construction will be terminated and the sequencer will move on to the next descriptor in the table ...
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... ARINC 429 Immediate Transmit Option The Host CPU may instruct the HI-3200 to transmit an ARINC 429 message immediately using a special SPI command. The SPI command selects the transmit channel and provides the four bytes of data to be sent as a 32-bit ARINC 429 message. ...
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... CAN BUS TRANSMIT OPERATION The HI-3200 is able to transmit CAN frames via an external HI-3110 CAN controller / transceiver IC. CAN frames may be loaded for immediate transmission from the host CPU pre-programmed sequence using the integrated CAN frame scheduler. CAN BUS Transmit Scheduler CAN frames to be transmitted are constructed and launched from the CAN Bus transmit scheduler ...
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... Frame Descriptor. Each descriptor consists of one “Descriptor Header Byte” and from additional descriptor bytes depending upon, the descriptor type (type and the data payload length. A special descriptor header marks the end of the descriptor table. HI-3200, HI-3201 Channel Repetition Period ...
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... NOTE: Bit 7 should be set to the value of the reserved bit “r1” of the CAN frame. Type 1 CAN Transmit Descriptor Frame Format Type 1 CAN transmit descriptors are used when transmitting frames using CAN Identifier and Data payload values defined explicitly by the HI-3200 Host CPU or Auto-initialization EEPROM. The descriptor format is as follows: HI-3200, HI-3201 ...
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... CAN ID1 Value Byte CAN ID1 Action Byte Type 3 Descriptor Header Byte Type 3 Descriptor Block HI-3200, HI-3201 CAN Data Byte values may be directly loaded from the host CPU / Auto-initialization EEPROM, or are read from the ARINC 429 Received Data RAM or CAN Bus Received Data RAM as indexed by the two data source descriptor bytes (op-code byte and index byte) ...
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... LLLLLLLL 0X1 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 XBBBB NNNNNNNN 111 XBBBB NNNNNNNN HI-3200, HI-3201 Op-Code Index LSB MSB ACTION BYTE Description Immediate data. The value contained in the descriptor value data byte is loaded into this byte position of the CAN Frame to be transmitted. ...
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... CAN Bus Immediate Transmit Option The Host CPU may instruct the HI-3200 to transmit an CAN frame immediately using a special SPI command. The SPI command describes the CAN frame with SPI data bytes. The bit format of the data bytes is exactly the same as a Type 1 transmit descriptor, except the Type Field of the header byte is “ ...
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... The RAMFAIL Interrupt is not maskable. HI-3200, HI-3201 2. Clear Data Memory In Modes and 7, the HI-3200 automatically clears all memory locations in the address range 0x0000 to 0x33FF. This is the space reserved for ARINC 429 and CAN message data. Configuration tables and HI-3200 registers are not affected ...
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... By-pass mode is exited at the first rising edge of the RUN pin. Further toggling of the RUN pin will not re-engage the by-pass mode. Since the host does not have access to internal HI-3200 registers prior to RUN going high, the user must first initialize these registers prior to entering Mode 6. ...
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... Clear Configuration Tables (0x3400 - 0xFFFF) Auto-Initialize from No EEPROM Enable SPI By-Pass No MODE 0 HI-3110 Initialize Yes Disable SPI By-Pass n/a HI-3200, HI-3201 RESET driven to “1” Stop execution, READY => 0 RESET STATE RESET driven to “0” Sample MODE2:0 inputs MODE 1 MODE 2 MODE 3 No Yes Yes ...
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... There are four fault Interrupt bits in the PIR. Fault Interrupts are not maskable, and their Interrupt Mask bits are fixed at a “1”. COPYERR is set when the HI-3200 detects a mismatch between RAM and EEPROM after attempting to program the Auto-initialization EEPROM. AUTOERR is set when the Auto-Initialization EEPROM ...
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... CANRX R/W 0 INT is asserted if this bit is a “1” and the PIR CANRX bit is set 0 CTXRDY R/W 0 INT is asserted if this bit is a “1” and the PIR CTXRDY bit is set CAN INTERRUPT ADDRESS REGISTER (Address 0x800B) HI-3200, HI-3201 MSB ...
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... RAM BUILT-IN SELF-TEST The HI-3200 offers a built-in self-test (BIST) feature which can be used to check RAM integrity. The BIST Control/Status Register is used to control the BIST function. All tests are destructive, overwriting data present before test commencement. BIST CONTROL/STATUS REGISTER (Address 0x8070) This register controls RAM built-in self-test. Bits 0,1 are Read Only. The remaining bits in this register are Read-Write but can be written only in MODE2:0 = 0x04 ...
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... RBSTRT bit 3 is set. LOWER BIST FAIL ADDRESS REGISTER (Address 0x8071) UPPER BIST FAIL ADDRESS REGISTER (Address 0x8072) HI-3200, HI-3201 f. Write then read and verify 0x0F g. Write then read and verify 0xF0 h. Write then read and verify 0x00 I ...
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... SCK signal. There is no configuration setting in the HI-3200 to select SPI Mode 0 or Mode 3 because compatibility is automatic. Beyond this point, the HI-3200 data sheet only shows the SPI Mode 0 SCK signal in timing diagrams. The SPI protocol transfers serial data as 8-bit bytes. Once ...
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... SCK SPI Mode 0 MSB SI Command Byte High FIGURE 2. Single-Byte Read From RAM or a Register SCK SPI Mode 0 MSB SI Command Byte High HI-3200, HI-3201 LSB MSB Data Byte LSB ...
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... Further, these register addresses will not provide meaningful data in response to read commands. RAM and Register Indirect Addressing Refer to the HI-3200 SPI command set shown in Table 1. SPI commands other than fast-access use an address pointer to indicate the address for read or write transactions. This sixteen-bit memory address pointer (MAP) must be initialized before any non-fast-access read or write operation ...
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... HI-3200, HI-3201 Op Code 0x90 Writes a CAN frame to the CAN transmit scheduler for immediate transmission. Op Code 100101TT Writes an ARINC 429 message to ARINC 429 transmit scheduler TT for immediate transmission, where TT represents the channel number ...
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... HOST SPI BY-PASS When the HI-3200 is reset and initialization Mode 6 is selected (by setting MODE2:0 inputs to “110”), the SPI by- pass function is enabled when the device is in the idle state. SPI By-Pass allows the host CPU to communicate directly with the HI-3110 CAN controller via its dedicated SPI interface, by-passing the HI-3200 ...
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... IDLE state. Taking the PROG pin low initiates the cycle. The READY pin goes low, and the contents of the HI-3200 memory and registers are copied to the EEPROM. When copying is complete, the HI-3200 executes a byte-by-byte comparison of the EEPROM and its own register / memory contents ...
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... Supply Current Min. Input Voltage (HI) Max. Input Voltage (LO) Pull-Up / Pull-Down Current Min. Output Voltage (HI) Max. Output Voltage (LO) HI-3200, HI-3201 RECOMMENDED CONDITIONS -0 +5 +3.6 V 1.0 W 275°C for 10 sec. 175°C -65°C to +150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device ...
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... SPI SI Data hold time after SCK rising edge SO high-impedance after CE SCLK SCKH SCKL SCLK SO Hi Impedance HI-3200, HI-3201 SYMBOL SCK clock period inactive between SPI instructions SCK high time SCK low time SO valid after SCK falling edge CE inactive SERIAL INPUT TIMING DIAGRAM t CES t DH MSB ...
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... PIN CONFIGURATION FOR HI-3200, 64-PIN QFN PACKAGE Notes 1 . All VDD and GND pins must be connected. 2. See data sheet page 1 for HI-3200, 64-Pin PQFP Package Configuration. SCANSHIFT HI-3200, HI-3201 AACK 1 CGP2 2 AINT 3 CSTAT 4 5 ARX2N 6 ARX3P 7 VDD 8 HI-3200PCx GND 9 ARX3N 10 ARX4P 11 ARX4N 12 ...
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... PIN CONFIGURATION FOR HI-3201, 80-PIN PQFP PACKAGE Notes 1 . All VDD and GND pins must be connected. 2. See data sheet page 1 for HI-3200, 64-Pin PQFP Package Configuration. AACK ARXBIT6 CGP2 AINT ARXBIT7 CSTAT SCANSHIFT ARX2N ARX3P VDD 10 VDD 11 GND 12 GND 13 ARX3N 14 ARX4P 15 ARX4N 16 ...
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... ORDERING INFORMATION HI-3200Px x x PART NUMBER Blank F PART NUMBER PART NUMBER PQ PC HI-3201PQ x F PART NUMBER F PART NUMBER PART NUMBER PQ HI-3200, HI-3201 PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE FLOW -40°C TO +85°C I -55° ...
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... REVISION HISTORY Document Rev. Date Description of Change DS3200 New 5/4/11 Initial Release. HI-3200, HI-3201 HOLT INTEGRATED CIRCUITS 56 ...
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... BSC SQ (10.00) .055 .002 ± (1.40 ± .05) .004 .002 ± (0.10 ± .05) The metal heat sink pad on the bottom of the package is electrically isolated from the chip. It can be left floating or connected to VDD or GND .281 ± .003 (7.125 ± .075 ) .016 ± .004 (0.40 ± .10 ) .008 typ (0 ...
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PIN PLASTIC QUAD FLAT PACK (PQFP) .472 (12.00) BSC SQ See Detail A .063 max (1.60) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) PACKAGE DIMENSIONS .394 BSC SQ ...