am42dl6404g Meet Spansion Inc., am42dl6404g Datasheet
am42dl6404g
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am42dl6404g Summary of contents
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... Am42DL6404G Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
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... PRELIMINARY Am42DL6404G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640G 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — Access time as fast Package — ...
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... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Am42DL6404G March 20, 2002 ...
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... Operation Timings.......................................................................... 51 Read Cycle ............................................................................. 52 Figure 28. SRAM Read Cycle—Address Controlled...................... 52 Figure 29. SRAM Read Cycle ........................................................ 53 Write Cycle ............................................................................. 54 Figure 30. SRAM Write Cycle—WE# Control ................................ 54 Figure 31. SRAM Write Cycle—CE1#s Control ............................. 55 Figure 32. SRAM Write Cycle—UB#s and LB#s Control............... 56 Flash Erase And Programming Performance . . 57 Am42DL6404G vs. Frequency............................................ 37 3 ...
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... Package Pin Capacitance . . . . . . . . . . . . . . . . . . 57 flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 57 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 58 Figure 33. CE1#s Controlled Data Retention Mode........................ Figure 34. CE2s Controlled Data Retention Mode......................... 58 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 59 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 60 Am42DL6404G March 20, 2002 ...
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... March 20, 2002 Am42DL6404G Flash Memory RY/BY# 64 MBit Flash Memory DQ15/A–1 to DQ0 V s CCQ SS SSQ 4 MBit DQ15/A–1 to DQ0 Static RAM Am42DL6404G SRAM DQ15/A–1 to DQ0 5 ...
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... CE# COMMAND REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux OE# BYTE# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 Am42DL6404G DQ15–DQ0 Mux March 20, 2002 ...
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... DQ7 DQ11 NC DQ5 DQ14 The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am42DL6404G Flash only A10 NC SRAM only B10 NC Shared D9 A15 E9 A21 F9 F10 G10 A16 ...
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... SRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 18 A17–A0 A21–A18, A-1 CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf Am42DL6404G DQ15–DQ0 RY/BY# March 20, 2002 ...
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... TAPE AND REEL inches inches TEMPERATURE RANGE I = Industrial (– +85 C) SPEED OPTION See Product Selector Guide and Valid Combinations PROCESS TECHNOLOGY G = 0.17 µm SRAM DEVICE DENSITY Mbits Order Number Am42DL6404G70I Am42DL6404G85I Am42DL6404G Valid Combinations Package Marking T, S M42000002U T, S M42000002V 9 ...
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... 9.0 ± 0 Don’t Care, SADD = Flash Sector Address the same time. IH the boot sectors protection will be removed the two outermost boot sector protection depends on IH Am42DL6404G IH WP#/ACC DQ7– DQ15– RESET# (Note 4) DQ0 X H L/H D ...
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... Don’t Care, SADD = Flash Sector Address Data In Data Out IN OUT at the same time. IH the boot sectors protection will be removed the two outermost boot sector protection depends on IH Am42DL6404G SS WP#/ACC DQ7– DQ15– RESET# (Note 4) DQ0 DQ8 H L/H D High-Z OUT ...
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... Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location Am42DL6404G on this pin, the device auto- HH must not be asserted on HH March 20, 2002 ...
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... ACC Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input disabled. The output pins are placed in the high impedance state. Am42DL6404G , the RP ±0.3 V, the device SS f). If RESET# is CC4 ±0.3 V, the standby cur- SS (during Embedded Algorithms) ...
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... Am42DL6404G (x16) Address Range 00000h–00FFFh 01000h–01FFFh 02000h–02FFFh 03000h–03FFFh 04000h–04FFFh 05000h–05FFFh 06000h–06FFFh 07000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h– ...
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... Am42DL6404G (x16) Address Range 80000h–87FFFh 88000h–8FFFFh 90000h–97FFFh 98000h–9FFFFh A0000h–A7FFFh A8000h–AFFFFh B0000h–B7FFFh B8000h–BFFFFh C0000h–C7FFFh C8000h–CFFFFh D0000h–D7FFFh D8000h–DFFFFh E0000h– ...
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... Am42DL6404G (x16) Address Range 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h– ...
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... Table 4. Bank Address A21–A19 001, 010, 011 100, 101, 110 Table 5. SecSi Sector Addresses Sector Size 256 bytes 000000h–0000FFh Am42DL6404G (x16) Address Range 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h– ...
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... To change 256 (4x64) Kbytes data in protected sectors efficiently, the temporary 256 (4x64) Kbytes sector unprotect function is available. See “Temporary 256 (4x64) Kbytes Sector Unprotect”. Am42DL6404G Sector/ A21–A12 Sector Block Size 01110XXXXX 256 (4x64) Kbytes 01111XXXXX ...
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... Notes: 1. All protected sectors unprotected (If WP#/ACC = V sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am42DL6404G V . During this mode, formerly protected ID is removed from the RE sectors 0, 1, 140, and ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am42DL6404G START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... V and power-down transitions, or from system noise. Low V Write Inhibit CC When V is less than V CC cept any write cycles. This protects data during V Am42DL6404G This IH ID power- the device does not ac- LKO CC ...
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... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am42DL6404G Description March 20, 2002 ...
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... Erase Block Region 3 Information 0020h (refer to the CFI specification or CFI publication 100) 0000h 0000h 0000h Erase Block Region 4 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h Am42DL6404G Description pin present) PP pin present µs N µ s (00h = not supported) ...
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... Not supported Supported Bank Organization 0004h 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information 0017h X = Number of Sectors in Bank 1 Bank 2 Region Information 0030h X = Number of Sectors in Bank 2 Bank 3 Region Information 0030h X = Number of Sectors in Bank 3 Bank 4 Region Information 0017h X = Number of Sectors in Bank 4 Am42DL6404G Description March 20, 2002 ...
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... The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- Am42DL6404G 25 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Am42DL6404G any operation HH March 20, 2002 ...
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... When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading Am42DL6404G 27 ...
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... Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 12 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am42DL6404G START Embedded Erase algorithm in progress Yes March 20, 2002 ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am42DL6404G Fourth Fifth Sixth Addr Data ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am42DL6404G Yes No Yes Yes No ...
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... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm Am42DL6404G No Yes Yes No Yes ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits. Am42DL6404G March 20, 2002 ...
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... The device outputs array data if the system addresses a non-busy bank. March 20, 2002 Table 13. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am42DL6404G DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... Operating ranges define those limits between which the functionality of the device is guaranteed +0.8 V –0.5 V –2 Figure 7. Maximum Negative Overshoot Waveform + –2 2.0 V Figure 8. Maximum Positive Overshoot Waveform Am42DL6404G March 20, 2002 ...
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... 4.0 mA min I = –2.0 mA min I = –100 µ min . max ACC Am42DL6404G Min Typ Max Unit 1 0.2 5 0 ...
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... OH CE1 CE2 = V , Other IH IL inputs = CE1#s V – 0.2 V, CE2 V – 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = Other input = +2 Am42DL6404G Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ 0.4 V 2 µA –0.2 ...
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... Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note March 20, 2002 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am42DL6404G 3000 3500 4000 3 ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am42DL6404G 70, 85 Unit 1 TTL gate 0.0–3 ...
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... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating March 20, 2002 Test Setup — t CCR t CCR Between SRAM to Flash Am42DL6404G All Speeds Unit Min CCR t CCR 39 ...
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... Test Setup CE# Read Toggle and Data# Polling Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 14. Read Operation Timings Am42DL6404G Speed 70 85 Unit Min 70 85 Max Max Max 30 40 Max 30 35 Max 30 ...
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... RESET# March 20, 2002 Description Max Max Min Min Min Min Ready Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings Am42DL6404G All Speed Options Unit 20 s 500 ns 500 ...
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... Data Output (DQ7–DQ0) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am42DL6404G Speed 70 85 Unit Data Output (DQ7–DQ0) Address Input Data Output (DQ14–DQ0) March 20, 2002 ...
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... Write Recovery Time from RY/BY Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. March 20, 2002 Byte Word Am42DL6404G Speed 70 85 Unit Min Min 0 ns ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am42DL6404G Read Status Data (last two cycles WHWH1 D Status OUT VHH March 20, 2002 ...
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... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings March 20, 2002 SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am42DL6404G Read Status Data WHWH2 In Complete Progress ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am42DL6404G Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data March 20, 2002 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am42DL6404G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 47 ...
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... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP Am42DL6404G All Speed Options Unit 500 ns 250 VIDR ...
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... For sector protect For sector unprotect SADD = Sector Address. Figure 26. Sector/Sector Block Protect and March 20, 2002 Valid* Valid* 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am42DL6404G Valid* Verify 40h Status 49 ...
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... Word or Byte (Note Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Byte Word Am42DL6404G Speed 70 85 Unit Min Min 0 ns Min ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am42DL6404G PA DQ7# D OUT 51 ...
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... Figure 28. SRAM Read Cycle—Address Controlled Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB Am42DL6404G Speed Unit ...
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... March 20, 2002 CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am42DL6404G BHZ t OHZ 53 ...
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... (See Note (See Note 4) High-Z t WHZ applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42DL6404G Speed Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low Am42DL6404G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... AS t (See Note 4) WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low Am42DL6404G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT Test Conditions Am42DL6404G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... V (Note 3.0 V, CE1#s V – 0 (Note 1) See data retention waveforms 0.2 V (CE2s controlled). Data Retention Mode t SDR CE1 0 Data Retention Mode t SDR CE2s < 0.2 V Am42DL6404G Min Typ Max Unit 1.5 3.3 V 1.0 10 µA (Note RDR t RDR March 20, 2002 ...
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... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm March 20, 2002 Am42DL6404G 59 ...
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... Revision A+1 (March 20, 2002) SRAM DC and Operating Characteristics Changed maximum specifications for I Added V and Figure 30, SRAM Write Cycle—WE# Control Corrected t in data out waveform Am42DL6404G s and SB1 and corresponding notes to table. . WHZ March 20, 2002 ...