k4t51043qb-zcd5 Samsung Semiconductor, Inc., k4t51043qb-zcd5 Datasheet - Page 16

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k4t51043qb-zcd5

Manufacturer Part Number
k4t51043qb-zcd5
Description
512mb B-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
For purposes of IDD testing, the following parameters are utilized
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) and t FAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D
512Mb B-die DDR2 SDRAM
t RRD(IDD)-x4/x8
t RRD(IDD)-x16
t RASmin(IDD)
Parameter
t RCD(IDD)
t RFC(IDD)
t RC(IDD)
t CK(IDD)
t RP(IDD)
CL(IDD)
DDR2-533
Page 16 of 28
4-4-4
3.75
105
7.5
15
60
10
45
15
4
DDR2-400
3-3-3
105
7.5
15
55
40
15
10
3
5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
DDR2 SDRAM
Rev. 1.5 July 2005

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