k4h560838f-uccc ETC-unknow, k4h560838f-uccc Datasheet - Page 8

• Manufacturer Part Number: k4h560838f-uccc
• Description: Ddr Sdram Ddr Sdram 256mb F-die X8, X16
• Manufacturer: ETC-unknow

Command Truth Table
DDR SDRAM 256Mb F-die (x8, x16)
Note :
Register
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Active Power Down
Precharge Power Down Mode
DM(UDM/LDM for x16 only)
No operation (NOP) : Not defined
1. OP Code : Operand Code. A
2. EMRS/MRS can be issued only at all banks precharge state.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA
5. If A
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
A new command can be issued 2 clock cycles after EMRS or MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If BA
If BA
If both BA
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
0
10
~ BA
0
0
/AP is "High" at row precharge, BA
is "High" and BA
is "Low" and BA
COMMAND
1
0
0
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
: Bank select addresses.
and BA
and BA
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
1
1
is "High" at read, write, row active and precharge, bank C is selected.
is "Low" at read, write, row active and precharge, bank B is selected.
Entry
Entry
Entry
Exit
Exit
Exit
0
~ A
12
CKEn-1 CKEn
& BA
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
and BA
0
~ BA
H
H
H
H
X
X
L
X
X
X
X
X
L
L
X
1
1
are ignored and all banks are selected.
: Program keys. (@EMRS/MRS)
CS
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
RP
after the end of burst.
RAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
L
X
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
L
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
BA0,1 A10/AP
V
V
V
V
X
Rev. 1.1 August. 2003
OP CODE
OP CODE
H
H
H
L
L
L
DDR SDRAM
Row Address
X
X
X
X
X
X
X
A11, A12
A0 ~ A9,
Address
Address
Column
Column
X
Note
1, 2
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9