mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet
mt18lsdf6472y-133
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mt18lsdf6472y-133 Summary of contents
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... Synchronous DRAM Module MT18LSDF6472 – 512MB For the latest data sheet, refer to Micron’s Web site: Features • 168-pin, dual in-line memory module (DIMM) • PC133-compliant • Registered inputs with one-clock delay • Phase-lock loop (PLL) clock driver to reduce loading • Utilizes 133 MHz SDRAM components • ...
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... Part Numbers Part Number MT18LSDF6472G-13E__ MT18LSDF6472Y-13E__ MT18LSDF6472G-133__ MT18LSDF6472Y-133__ Notes: 1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT18LSDF6472G-133B1. PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a SDF18C64x72G.fm - Rev. E 9/05 EN 512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM ...
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Pin Assignments and Descriptions Table 4: Pin Assignments 168-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol CB1 DQ0 ...
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... SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Input Serial clock for presence-detect: SCL is used to synchronize the presence- detect data transfer to and from the module. Input Presence-Detect address inputs: These pins are used to configure the presence-detect device. Input Register enable ...
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... Functional Block Diagram Per industry standard, Micron modules utilize various component speed grades, as ref- erenced in the module part number guide at ing.html. Standard modules use the following SDRAM devices: MT48LC64M4A2FB (512MB). Lead-free modules use the following SDRAM devices: MT48LC64M4A2BB (512MB). ...
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Figure 3: Functional Block Diagram RAS# CAS# CKE0 WE# A0–A12 BA0 BA1 S0#, S2# DQMB0–DQMB7 10K U18 V DD REG PLL CLK Note: All resistor values are 10Ω unless otherwise specified. PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a SDF18C64x72G.fm - Rev. E 9/05 EN ...
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... READ or WRITE command are used to select the starting device column location for the burst access. SDRAM modules provide for programmable read or write locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. ...
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... DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational pro- cedures other than those specified may result in undefined operation ...
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The ordering of accesses within a burst is determined by BL, the burst type and the start- ing column address, as shown in Table 6. Burst Type Accesses within a given burst may be programmed to be either sequential or ...
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Table 6: Burst Definition Table Burst Length Full Page Notes: 1. For full-page accesses 2,048. 2. For A1–A9, A11 select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = ...
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Figure 5: CAS Latency Diagram COMMAND COMMAND CAS Latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two ...
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Figure 6: CAS Latency Table Registered mode adds one clock cycle to CL Speed -13E -133 Commands Table 7, provides a quick reference of available commands. This is followed by written description of each command. For a more detailed description ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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... Input capacitance: CK Input/Output capacitance: DQ Table 11: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 31; notes appear on pages 16 and 17 Module AC timing parameters comply with PC133 Design Specs, based on component parameters AC Characteristics Parameter Access time from CLK (pos.edge) Address hold time Address setup time ...
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Table 12 Functional Characteristics Notes 11, 31; notes appear on pages 16 and 17 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or ...
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Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used ...
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... RC - 33. This AC timing function will show an extra clock cycle when input register is in regis- tered mode. 34. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a SDF18C64x72G.fm - Rev. E 9/05 EN 512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM t WR, and PRECHARGE commands) ...
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PLL and Register Specifications Table 13: Register Timing Requirements and Switching Characteristics Register Symbol f clock t Propagation delay, Single rank pd1 SSTL t Propagation delay, Dual rank pd2 bit pattern by JESD82 Table ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 8, and Figure ...
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Figure 9: Definition of Start and Stop SCL SDA Figure 10: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 15: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 11: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT Table 17: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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Table 18: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time ...
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... Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of row addresses 4 Number of column addresses 5 Number of module ranks 6 Module data width 7 Module data width (continued) 8 Module voltage interface levels t 9 SDRAM cycle time SDRAM access from clock, ...
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... ECC, SR): 168-PIN SDRAM RDIMM = +3.3V ±0.3V DD Entry (Version 66ns (-13E) 71ns (-133) MICRON 100 MHz (-13E/ -133) t RAS used for -13E modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 24 Serial Presence-Detect MT18LSDF6472 REV. 2.0 02 -13E ...
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Figure 12: 168-Pin DIMM Dimensions – Standard PCB 0.079 (2.00) R (2X 0.118 (3.00) (2X) 0.18 (3.00) 0.250 (6.35) PIN 1 0.118 (3.00) U12 U13 U14 PIN 168 Note: All dimensions are in inches (millimeters); PDF: 09005aef80a2e32f/Source: ...
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Figure 13: 168-Pin DIMM Dimensions – Low-Profile 0.079 (2.00) R (2X 0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) PIN 1 0.118 (3.00) U12 U13 U14 PIN 168 Note: All dimensions are in inches (millimeters); 8000 S. Federal ...