mt16vddf6464hy-40b Micron Semiconductor Products, mt16vddf6464hy-40b Datasheet - Page 7

• Manufacturer Part Number: mt16vddf6464hy-40b
• Description: 512mb, 1gb X64, Dr Pc3200 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

General Description
Serial Presence-Detect Operation
Table 6:
PDF: 09005aef80b57837/Source: 09005aef80b577fa
DDAF16C64_128x64H.fm - Rev. E 10/06 EN
CAS Latency (CL) Table
The MT16VDDF6464H and MT16VDDF12864H are high-speed CMOS, dynamic
random-access, 512MB and 1GB memory modules organized in a x64 configuration.
DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
Speed
-40B
512MB, 1GB: (x64, DR) PC3200 200-Pin DDR SODIMM
75 ≤ f ≤ 133
CL = 2
7
Allowable Operating Clock Frequency (MHz)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
75 ≤ f ≤ 167
CL = 2.5
General Description
©2004 Micron Technology, Inc. All rights reserved.
133 ≤ f ≤ 200
CL = 3
2
C