sri4k STMicroelectronics, sri4k Datasheet - Page 17
sri4k
Manufacturer Part Number
sri4k
Description
13.56 Mhz Short-range Contactless Memory Chip With 4096-bit Eeprom And Anticollision Functions
Manufacturer
STMicroelectronics
Datasheet
1.SRI4K.pdf
(49 pages)
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SRI4K
4.3
Figure 16. Count down example (binary format)
The counter with block address 6 controls the Reload command used to reset the resettable
OTP area (addresses 0 to 4). Bits b
of these 11 bits is updated, the SRI4K detects the change and adds an Erase cycle to the
WRITE_BLOCK command for locations 0 to 4 (see the
The Erase cycle remains active until a POWER-OFF or a SELECT command is issued. The
SRI4K’s resettable OTP area can be reloaded up to 2 047 times (2
EEPROM Area
The 121 blocks between addresses 7 and 127 are EEPROM blocks of 32 bits each (484
Bytes in total). (See
the READ_BLOCK and WRITE_BLOCK commands. The WRITE_BLOCK command for the
EEPROM area always includes an Auto-Erase cycle prior to the Write cycle.
Blocks 7 to 15 can be Write-protected. Write access is controlled by the 8 bits of the
OTP_Lock_Reg located at block address 255 (see “OTP_Lock_Reg” for details). Once
protected, these blocks (7 to 15) cannot be unprotected.
Initial data
1-unit decrement
1-unit decrement
1-unit decrement
8-unit decrement
Increment not allowed
Figure 17
b31
1
1
1
1
1
1
...
...
...
...
...
...
for a map of the area.) These blocks can be accessed using
1
1
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1
31
to b
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1
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1
1
21
1
1
1
1
1
1
act as an 11-bit Reload counter; whenever one
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1
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1
1
1
1
1
1
1
1
1
“Resettable OTP
1
1
1
1
1
1
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1
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1
1
1
1
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1
11
-1).
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1
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1
Memory mapping
area” paragraph).
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1
0
1
1
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1
1
1
0
1
1
0
0
0
0
ai07661
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0
0
0
17/49
b0