lamxo640c Lattice Semiconductor Corp., lamxo640c Datasheet
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LA-MachXO Automotive Family Data Sheet DS1003 Version 01.5, November 2007 ...
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... Lead-Free ftBGA (19x19 mm) © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. ® The ispLEVER design tools from Lattice allow complex designs to be efficiently implemented ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Figure 2-1. Top View of the LA-MachXO1200 Device sysMEM Embedded Block RAM (EBR) sysCLOCK PLL JTAG Port 1. Top view of the LA-MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks. Figure ...
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Lattice Semiconductor Figure 2-3. Top View of the LA-MachXO256 Device JTAG Port Programmable Function Units with RAM (PFUs) PFU Blocks The core of the LA-MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, ...
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Lattice Semiconductor There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists ...
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Lattice Semiconductor Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of ...
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Lattice Semiconductor Figure 2-6. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK ROM16x1 AD0 AD1 AD2 AD3 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading ...
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Lattice Semiconductor The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock/Control ...
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Lattice Semiconductor Figure 2-8. Primary Clocks for LA-MachXO1200 and LA-MachXO2280 Devices Routing Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock sources come from dual function clock ...
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Lattice Semiconductor sysCLOCK Phase Locked Loops (PLLs) The LA-MachXO1200 and LA-MachXO2280 provide PLL support. The source of the PLL input divider can come from an external pin or from internal routing. There are four sources of feedback signals to the ...
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Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing I PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from CLKFB CLKINTFB port RST I “1” to ...
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Lattice Semiconductor Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so ...
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Lattice Semiconductor The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current address) ...
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Lattice Semiconductor Figure 2-13. Memory Core Reset RSTA RSTB GSRN For further information on the sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR ...
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Lattice Semiconductor PIO Groups On the LA-MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO cells. PIO groups with four IOs are placed on the left ...
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Lattice Semiconductor output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17 shows the LA-MachXO PIO logic. The tristate control signal is multiplexed from the output data signals and their ...
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Lattice Semiconductor of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The PCI clamp is enabled after V CC figured. The two pads in the pair are described as “true” and ...
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Lattice Semiconductor Table 2-8. I/O Support Device by Device LA-MachXO256 Number of I/O Banks 2 Single-ended (all I/O Banks) Type of Input Buffers Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers Differential Output All I/O Banks ...
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Lattice Semiconductor Table 2-10. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain 3 PCI33 Differential Interfaces 1, 2 LVDS 2 ...
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Lattice Semiconductor Figure 2-18. LA-MachXO2280 Banks V CCIO7 GND V CCIO6 GND Figure 2-19. LA-MachXO1200 Banks V CCIO7 GND V CCIO6 GND LA-MachXO Automotive Family Data Sheet Bank 0 Bank ...
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Lattice Semiconductor Figure 2-20. LA-MachXO640 Banks V CCO3 GND Figure 2-21. LA-MachXO256 Banks GND V CCO1 Hot Socketing The LA-MachXO automotive devices have been carefully designed to ensure predictable behavior during power- up and power-down. Leakage into I/O pins is ...
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Lattice Semiconductor with the rest of the system. These capabilities make the LA-MachXO ideal for many multiple power supply and hot-swap applications. Sleep Mode The LA-MachXO “C” devices (V CC dramatically during periods of system inactivity. Entry and exit to ...
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Lattice Semiconductor Device Configuration All LA-MachXO devices contain a test access port that can be used for device configuration and programming. The non-volatile memory in the LA-MachXO can be configured in two different modes: • In IEEE 1532 mode via ...
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Lattice Semiconductor Figure 2-22. LA-MachXO Configuration and Programming Port Background Mode Program in seconds Non-Volatile Memory Space Density Shifting The LA-MachXO family has been designed to enable density migration in the same package. Furthermore, the architecture ensures a high success ...
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... PD BH © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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Lattice Semiconductor LA-MachXO1200 and LA-MachXO2280 Hot Socketing Specifications Symbol Parameter Non-LVDS General Purpose sysIOs I Input or I/O Leakage Current DK LVDS General Purpose sysIOs I Input or I/O Leakage Current DK_LVDS 1. Insensitive to sequence CC, ...
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Lattice Semiconductor Supply Current (Sleep Mode) Symbol Parameter I Core Power Supply CC I Auxiliary Power Supply CCAUX I Bank Power Supply CCIO 1. Assumes all inputs are configured as LVCMOS and held at the VCCIO or GND. 2. Frequency ...
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Lattice Semiconductor Initialization Supply Current Symbol Parameter I Core Power Supply CC Auxiliary Power Supply I CCAUX V = 3.3V CCAUX I Bank Power Supply CCIO 1. For further information on supply current, please see details of additional technical documentation ...
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Lattice Semiconductor Programming and Erase Flash Supply Current Symbol Parameter I Core Power Supply CC Auxiliary Power Supply I CCAUX V = 3.3V CCAUX I Bank Power Supply CCIO 1. For further information on supply current, please see details of ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL 3 PCI 1, 2 LVDS 1 LVPECL 1 BLVDS 1 RSDS 1. Inputs on chip. Outputs are implemented with the addition of ...
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Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.42 ...
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Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Symbol Parameter Description V V Input Voltage INP, INM V Differential Input Threshold THD V Input Common Mode Voltage CM I Input current IN V Output high voltage for ...
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Lattice Semiconductor Table 3-1. LVDS DC Conditions Parameter Z Output impedance OUT R Driver series resistor S R Driver parallel resistor P R Receiver termination T V Output high voltage OH V Output low voltage OL V Output differential voltage ...
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Lattice Semiconductor Table 3-2. BLVDS DC Conditions Symbol Z OUT R TLEFT R TRIGHT For input buffer, see LVDS table. LVPECL The LA-MachXO automotive family supports the differential LVPECL ...
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Lattice Semiconductor For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni- cal documentation at the end of the data sheet. RSDS The LA-MachXO automotive family supports the differential RSDS standard. The output standard ...
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Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Register-to-Register Performance Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter Embedded Memory Functions (1200 and 2280 ...
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Lattice Semiconductor LA-MachXO External Switching Characteristics Parameter General I/O Pin Parameters (Using Global Clock without PLL) t Best Case Best Case Clock to Output - From PFU CO t Clock to Data Setup - To PFU SU ...
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Lattice Semiconductor LA-MachXO Internal Timing Parameters Parameter PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU LSR_PFU ...
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Lattice Semiconductor LA-MachXO Family Timing Adders Buffer Type Input Adjusters 4 LVDS25 4 BLVDS25 4 LVPECL33 LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 4 PCI33 Output Adjusters LVDS25E 4 LVDS25 BLVDS25 LVPECL33 LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_14mA LVCMOS25_4mA ...
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Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics ...
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Lattice Semiconductor Flash Download Time Symbol Minimum CCAUX t (later of the two supplies) REFRESH to Device I/O Active JTAG Port Timing Specifications Symbol f TCK [BSCAN] clock frequency MAX t TCK [BSCAN] clock pulse width ...
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Lattice Semiconductor Switching Test Conditions Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Figure 3-5. Figure 3-6. Output Test Load, LVTTL ...
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... Applies to LA-MachXO “C” devices only. NC for “E” devices. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Pinout Information LAMXO640C/E 144 TQFP 256 ftBGA 74 113 159 29/10 42/21 30/11 40/20 24/9 36/18 30/13 40/20 LAMXO2280E 100 TQFP 144 TQFP 256 ftBGA 73 113 211 ...
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Lattice Semiconductor Power Supply and NC Signal VCC LAMXO256/640: 35, 90 LAMXO1200/2280: 17, 35, 66, 91 VCCIO0 LAMXO256: 60, 74, 92 LAMXO640: 80, 92 LAMXO1200/2280: 94 VCCIO1 LAMXO256: 10, 24, 41 LAMXO640: 60, 74 LAMXO1200/2280: 80 VCCIO2 LAMXO256: None LAMXO640: ...
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Lattice Semiconductor Power Supply and NC (Cont.) Signal VCC G7, G10, K7, K10 VCCIO0 LAMXO640: F8, F7, F9, F10 LAMXO1200/2280: F8, F7 VCCIO1 LAMXO640: H11, G11, K11, J11 LAMXO1200/2280: F9, F10 VCCIO2 LAMXO640: L9, L10, L8, L7 LAMXO1200/2280: H11, G11 ...
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Lattice Semiconductor LA-MachXO256 and LA-MachXO640 Logic Signal Connections: 100 TQFP LAMXO256 Ball Pin Number Function Bank 1 PL2A 1 2 PL2B 1 3 PL3A 1 4 PL3B 1 5 PL3C 1 6 PL3D 1 7 PL4A 1 8 PL4B 1 ...
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Lattice Semiconductor LA-MachXO256 and LA-MachXO640 Logic Signal Connections: 100 TQFP (Cont.) LAMXO256 Ball Pin Number Function Bank 42 GNDIO1 1 43 PB4A 1 44 PB4B 1 45 PB4C 1 46 PB4D 1 47 PB5A 1 48* SLEEPN - 49 PB5C ...
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Lattice Semiconductor LA-MachXO256 and LA-MachXO640 Logic Signal Connections: 100 TQFP (Cont.) LAMXO256 Ball Pin Number Function Bank 83 PT4C 0 84 GND - 85 PT4B 0 86 PT4A 0 87 PT3D 0 88 VCCAUX - 89 PT3C 0 90 VCC ...
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Lattice Semiconductor LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 100 TQFP LAMXO1200 Pin Ball Number Function Bank 1 PL2A 7 2 PL2B 7 3 PL3C 7 4 PL3D 7 5 PL4B 7 6 VCCIO7 7 7 PL6A 7 8 PL6B 7 ...
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Lattice Semiconductor LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 100 TQFP (Cont.) LAMXO1200 Pin Ball Number Function Bank 41 GND - 42 PB9A 4 43 PB9B 4 44 VCCIO4 4 45 PB10A 4 46 PB10B PB11A ...
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Lattice Semiconductor LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 100 TQFP (Cont.) LAMXO1200 Pin Ball Number Function Bank 80 VCCIO1 1 81 PT9E 1 82 PT9A 1 83 GND - 84 PT8B 1 85 PT8A 1 86 PT7D 1 87 PT6F ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 144 TQFP LAMXO640 Pin Ball Dual Number Function Bank Function Differential 1 PL2A 3 2 PL2C 3 3 PL2B 3 4 PL3A 3 5 PL2D 3 6 PL3B 3 7 PL3C ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 144 TQFP (Cont.) LAMXO640 Pin Ball Dual Number Function Bank Function Differential 51 TDI 2 TDI 52 VCC - 53 VCCAUX - 54 PB5A 2 55 PB5B 2 PCLKT2_1*** 56 PB5D ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 144 TQFP (Cont.) LAMXO640 Pin Ball Dual Number Function Bank Function Differential 101 PR3D 1 102 PR3C 1 103 PR3B 1 104 PR2D 1 105 PR3A 1 106 PR2B 1 107 ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA LAMXO640 Ball Ball Dual Number Function Bank Function Differential GND GNDIO3 3 VCCIO3 VCCIO3 PL3A PL3B ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LAMXO640 Ball Ball Dual Number Function Bank Function Differential J4 PL8A PL8B PL11A PL11B ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LAMXO640 Ball Ball Dual Number Function Bank Function Differential - - - - M10 PB6A PB6C 2 T R10 PB6D 2 C T10 PB7C 2 ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LAMXO640 Ball Ball Dual Number Function Bank Function Differential J13 PR8C 1 T GND GND - K14 PR8B 1 C J14 PR8A 1 T K15 PR7D 1 C ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LAMXO640 Ball Ball Dual Number Function Bank Function Differential E11 NC E10 NC D12 PT9D 0 C D11 PT9C 0 T A14 PT7F 0 C A13 PT7E 0 ...
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Lattice Semiconductor LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA (Cont.) LAMXO640 Ball Ball Dual Number Function Bank Function Differential A3 PT2B PT2A VCCIO0 VCCIO0 0 GND GNDIO0 0 A1 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA Ball Number Ball Function GND GNDIO7 VCCIO7 VCCIO7 D4 PL2A F5 PL2B B3 PL3A C3 PL3B E4 PL3C G6 PL3D A1 PL4A B1 PL4B F4 PL4C VCC VCC E3 PL4D D2 PL5A ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function G2 PL11A H2 PL11B L3 PL11C L5 PL11D H1 PL12A VCCIO6 VCCIO6 GND GNDIO6 J2 PL12B L4 PL12C L6 PL12D K2 PL13A K1 PL13B J1 PL13C VCC ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function T2 PL20B P6 TMS V1 PB2A U2 PB2B T3 PB2C N7 TCK R4 PB2D R5 PB3A T4 PB3B VCC VCC R6 PB3C P7 PB3D U3 PB4A T5 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function V10 PB9B N10 PB9C R10 PB9D P10 PB10F T10 PB10E U10 PB10D V11 PB10C U11 PB10B VCCIO4 VCCIO4 GND GNDIO4 T11 PB10A U12 PB11A R11 PB11B GND ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function GND GNDIO3 VCCIO3 VCCIO3 P15 PR20B N14 PR20A N15 PR19B M13 PR19A R15 PR18B T16 PR18A N16 PR17D M14 PR17C U17 PR17B VCC VCC U18 PR17A R17 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function J13 PR10C M18 PR10B L18 PR10A GND GNDIO2 VCCIO2 VCCIO2 H16 PR9D H14 PR9C K18 PR9B J18 PR9A J17 PR8D VCC VCC H18 PR8C H17 PR8B G17 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function E13 PT16D C15 PT16C F13 PT16B D14 PT16A A18 PT15D B17 PT15C A16 PT15B A17 PT15A VCC VCC D13 PT14D F12 PT14C C14 PT14B E12 PT14A C13 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function A10 PT8E VCCIO0 VCCIO0 GND GNDIO0 A9 PT8D C9 PT8C B9 PT8B F9 VCCAUX A8 PT8A B8 PT7D C8 PT7C VCC VCC A7 PT7B B7 PT7A A6 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function F16 GND H10 GND H11 GND H8 GND H9 GND J10 GND J11 GND J4 GND J8 GND J9 GND K10 GND K11 GND K17 GND K8 ...
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Lattice Semiconductor LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function G8 VCCIO0 G7 VCCIO0 * Supports true LVDS outputs. ** Primary clock inputs are single-ended. LA-MachXO Automotive Family Data Sheet LAMXO2280 Bank Dual Function 0 0 4-29 ...
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Lattice Semiconductor Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a ...
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... LUTs = 1200 2280 LUTs = 2280 Supply Voltage C = 1.8V/2.5V/3. 1.2V Note: Parts dual marked as described. Ordering Information Part Number LUTs LAMXO256C-3TN100E 256 LAMXO640C-3TN100E 640 LAMXO640C-3TN144E 640 LAMXO640C-3FTN256E 640 LAMXO256E-3TN100E 256 LAMXO640E-3TN100E 640 LAMXO640E-3TN144E 640 LAMXO640E-3FTN256E 640 LAMXO1200E-3TN100E 1200 LAMXO1200E-3TN144E 1200 LAMXO1200E-3FTN256E 1200 ...
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... PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Pinout Information Supplemental © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...