lamxo640c Lattice Semiconductor Corp., lamxo640c Datasheet - Page 2

• Manufacturer Part Number: lamxo640c
• Description: La-machxo Automotive Family Data Sheet
• Manufacturer: Lattice Semiconductor Corp.

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April 2006
Features
■ Non-volatile, Infinitely Reconfigurable
■ AEC-Q100 Tested and Qualified
■ Sleep Mode
■ TransFR™ Reconfiguration (TFR)
■ High I/O to Logic Density
■ Embedded and Distributed Memory
■ Flexible I/O Buffer
Table 1-1. LA-MachXO Automotive Family Selection Guide
LUTs
Dist. RAM (Kbits)
EBR SRAM (Kbits)
Number of EBR SRAM Blocks (9 Kbits)
V
Number of PLLs
Max. I/O
Packages
100-pin Lead-Free TQFP (14x14 mm)
144-pin Lead-Free TQFP (20x20 mm)
256-ball Lead-Free ftBGA (17x17 mm)
324-ball Lead-Free ftBGA (19x19 mm)
CC
Voltage
• Instant-on – powers up in microseconds
• Single chip, no external configuration memory
• Excellent design security, no bit stream to
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable
• Supports background programming of
• Allows up to 100x static current reduction
• In-field logic update while system operates
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
• Lead free/RoHS compliant packaging
• Up to 27.6 Kbits sysMEM™ Embedded Block
• Up to 7.5 Kbits distributed RAM
• Dedicated FIFO control logic
required
intercept
through JTAG port
non-volatile memory
RAM
Device
LA-MachXO Automotive Family Data Sheet
1.2/1.8/2.5/3.3V
LAMXO256E/C
256
2.0
78
78
0
0
0
1-1
■ sysCLOCK™ PLLs
■ System Level Support
Introduction
The LA-MachXO automotive device family is optimized
to meet the requirements of applications traditionally
addressed by CPLDs and low capacity FPGAs: glue
logic, bus bridging, bus interfacing, power-up control,
and control logic. These devices bring together the best
features of CPLD and FPGA devices on a single chip in
AEC-Q100 tested and qualified versions.
The devices use look-up tables (LUTs) and embedded
block memories traditionally associated with FPGAs for
flexible and efficient logic implementation. Through non-
volatile technology, the devices provide the single-chip,
1.2/1.8/2.5/3.3V
LAMXO640E/C
• Programmable sysIO™ buffer supports wide
• Up to two analog PLLs per device
• Clock multiply, divide, and phase shifting
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
• IEEE 1532 compliant in-system programming
range of interfaces:
power supply
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
640
159
113
159
6.0
74
0
0
0
LAMXO1200E
1200
6.25
211
113
211
9.2
1.2
73
1
1
DS1003 Introduction_01.0
Introduction
Data Sheet DS1003
LAMXO2280E
2280
27.6
271
113
211
271
7.5
1.2
73
3
2