s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 148

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
The order of the tasks listed above is not particularly
important. It is recommended that bus mastering be
enabled as the last step. Some applications may
choose to leave bus mastering enabled and start
transfers by writing a non-zero value to the transfer
count registers. This also works, provided the entire
transfer count is written in a single access. As a num-
ber of the configuration bits and the two enable bits
are all in the MCSR register, it may be most efficient
for the FIFO configuration bits to be set with the same
register access that enables bus mastering.
If interrupts are enabled, a host interrupt service rou-
tine is also required. The service routine determines
the source of the interrupt and resets the interrupt. As
mailbox registers may also be configured to generate
interrupts, the exact source of the interrupt is indicated
in the PCI Interrupt Control/Status Register (INTCSR).
Typically, the interrupt service routine is used to setup
the next transfer by writing new addresses and trans-
fer counts, but some applications may also require
other actions. If read transfer or write transfer com-
plete interrupts are enabled, master and target abort
interrupts are automatically enabled. These indicate a
transfer error has occurred. Writing a one to these bits
clears the corresponding interrupt.
148
7. Enable Bus Mastering. Once steps 1-6 are com-
MCSR
MCSR
INTCSR
INTCSR
INTCSR
INTCSR
pleted, the FIFO may operate as a PCI bus
master. Read and write bus master operation
may be independently enabled or disabled.
DS1527
Bit 14
Bit 10
Bit 21
Bit 20
Bit 19
Bit 18
Enable PCI to Add-On FIFO bus mas-
tering
Enable Add-On to PCI FIFO bus mas-
tering
Target abort caused interrupt
Master abort caused interrupt
Read transfer complete caused inter-
rupt
Write transfer complete caused inter-
rupt
Add-On Initiated FIFO Bus Mastering Setup For Add-
On initiated bus mastering, the Add-On sets up the
S5935 to perform bus master transfers. The following
t a s k s m u s t b e c o m p l e t e d t o s e t u p F I F O b u s
mastering:
AGCSTS
AINT
AINT
AGCSTS
AGCSTS
MCSR
MCSR
1. Define transfer count abilities. For Add-On initi-
2. Define interrupt capabilities. The PCI to Add-On
3. Reset FIFO flags. This may not be necessary, but
4. Define FIFO management scheme. These bits
ated bus mastering, transfer counts may be either
enabled or disabled. Transfer counts for read and
write operations cannot be individually enabled.
and/or Add-On to PCI FIFO can generate an
interrupt to the Add-On when the transfer count
reaches zero (if transfer counts are enabled).
if the state of the FIFO flags is not known, they
should be initialized.
define what FIFO condition must exist for the PCI
bus request (REQ#) to be asserted by the S5935.
This must be programmed through the PCI
interface.
Bit
Bit 14
Bit 13
Bit 9
Bit 28
Bit 25
Bit 26
15 Enable interrupt on read transfer
count equal zero
Enable interrupt on write transfer count
equal zero
PCI to Add-On FIFO management
scheme
Add-On to PCI FIFO management
scheme
Enable transfer count for read and
write bus master transfers
Reset Add-On to PCI FIFO flags
Reset PCI to Add-On FIFO flags
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book