pa28f004sc-120 Intel Corporation, pa28f004sc-120 Datasheet - Page 11

• Manufacturer Part Number: pa28f004sc-120
• Description: 8-mbit 1-mbit X 8 Flashfiletm Memory
• Manufacturer: Intel Corporation

Deep Power-Down
The 28F008SA offers a deep power-down feature
entered when RP
is 0 20 mA typical in deep power-down mode with
current draw through V
read modes
places output drivers in a high-impedence state and
turns off all internal circuits The 28F008SA requires
time t
erations) after return from powerdown until initial
memory access outputs are valid After this wakeup
interval normal operation is restored The Com-
mand User Interface is reset to Read Array and the
upper 5 bits of the Status Register are cleared to
value 10000 upon return to normal operation
During block erase or byte write modes RP
will abort either operation Memory contents of the
block being altered are no longer valid as the data
will be partially written or erased Time t
RP
other command can be written
This use of RP
with automated write erase devices When the sys-
tem comes out of reset it expects to read from the
flash memory Automated flash memories provide
NOTES
1 Bus operations are defined in Table 2
2 IA
3 SRD
4 Following the Intelligent Identifier command two read operations access manufacture and device codes
5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command
6 Commands other than those shown above are reserved by Intel for future device implementations and should not be
used
Read Array Reset
Intelligent Identifier
Read Status Register
Clear Status Register
Erase Setup Erase Confirm
Erase Suspend Erase Resume
Byte Write Setup Write
Alternate Byte Write Setup Write
BA
WA
WD
IID
e
e
e
goes to logic-high (V
PHQV
e
e
e
Identifier Address 00H for manufacturer code 01H for device code
Data read from Intelligent Identifiers
Address within the block being erased
Address of memory location to be written
Data to be written at location WA Data is latched on the rising edge of WE
Data read from Status Register See Table 4 for a description of the Status Register bits
Command
(see AC Characteristics-Read-Only Op-
RP -low deselects the memory
during system reset is important
is at V
PP
IL
IH
typically 0 1 mA During
) is required before an-
Current draw thru V
Cycles
Req’d
Bus
1
3
2
1
2
2
2
2
Table 3 Command Definitions
PHWL
Notes
2 3 4
2 3 5
2 3 5
1
3
2
after
low
CC
Operation Address Data Operation Address Data
Write
Write
Write
Write
Write
Write
Write
Write
status information when accessed during write
erase modes If a CPU reset occurs with no flash
memory reset proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data Intel’s
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
input In this application RP
same RESET
Intelligent Identifier Operation
The intelligent identifier operation outputs the manu-
facturer code 89H and the device code A2H for
the 28F008SA The system CPU can then automati-
cally match the device with its proper block erase
and byte write algorithms
The manufacturer- and device-codes are read via
the Command User Interface Following a write of
90H to the Command User Interface a read from
address location 00000H outputs the manufacturer
code (89H) A read from address 00001H outputs
the device code (A2H) It is not necessary to have
high voltage applied to V
identifiers from the Command User Interface
First Bus Cycle
WA
WA
BA
X
X
X
X
X
signal that resets the system CPU
FFH
B0H
90H
70H
50H
20H
40H
10H
PP
Read
Read
Write
Write
Write
Write
Second Bus Cycle
to read the intelligent
is controlled by the
WA
WA
BA
IA
X
X
28F008SA
SRD
D0H
D0H
WD
WD
IID
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