pa28f004sc-120 Intel Corporation, pa28f004sc-120 Datasheet - Page 14

• Manufacturer Part Number: pa28f004sc-120
• Description: 8-mbit 1-mbit X 8 Flashfiletm Memory
• Manufacturer: Intel Corporation

28F008SA
Byte Write Setup Write Commands
(40H or 10H)
Byte write is executed by a two-command sequence
The Byte Write Setup command (40H or 10H) is writ-
ten to the Command User Interface followed by a
second write specifying the address and data
(latched on the rising edge of WE ) to be written
The WSM then takes over controlling the byte write
and write verify algorithms internally After the two-
command byte write sequence is written to it the
28F008SA automatically outputs Status Register
data when read (see Figure 7 Byte Write Flowchart)
The CPU can detect the completion of the byte write
event by analyzing the output of the RY BY
the WSM Status bit of the Status Register Only the
Read Status Register command is valid while byte
write is active
When byte write is complete the Byte Write Status
bit should be checked If byte write error is detected
the Status Register should be cleared The internal
WSM verify only detects errors for ‘‘1’’s that do not
successfully write to ‘‘0’’s The Command User In-
terface remains in Read Status Register mode until
further commands are issued to it If byte write is
attempted while V
be set to ‘‘1’’ Byte write attempts while V
attempted
EXTENDED BLOCK ERASE BYTE
WRITE CYCLING
Intel has designed extended cycling capability into
its
28F008SA is designed for 100 000 byte write block
erase cycles on each of the sixteen 64-Kbyte
blocks Low electric fields advanced oxides and
minimal oxide area per cell subjected to the tunnel-
ing electric field combine to greatly reduce oxide
stress and the probability of failure A 20-Mbyte sol-
id-state drive using an array of 28F008SAs has a
MTBF (Mean Time Between Failure) of 33 3 million
hours
lent rotating disk technology
AUTOMATED BYTE WRITE
The 28F008SA integrates the Quick-Pulse program-
ming algorithm of prior Intel Flash devices on-chip
using the Command User Interface Status Register
and Write State Machine (WSM) On-chip integration
dramatically simplifies system software and provides
processor interface timings to the Command User
Interface and Status Register WSM operation inter-
nal verify and V
tored and reported via the RY BY
propriate Status Register bits Figure 7 shows a
(1)
(2000 files writes erase)
(200
14
k
Assumptions 10-Kbyte file written every 10 minutes (20-Mbyte array) (10-Kbyte file)
V
c
PPH
ETOX
(1)
10
6
produce spurious results and should not be
over 600 times more reliable than equiva-
file writes)
flash
PP
c
PP
c
high voltage presence are moni-
(10 min write)
e
memory
(100 000 cycles per 28F008SA block)
V
PPL
the V
c
technologies
(1 hr 60 min)
PP
output and ap-
Status bit will
PPL k
e
pin or
33 3
V
The
PP
c
e
10
200 million file writes
6
MTBF
system software flowchart for device byte write The
entire sequence is performed with V
write abort occurs when RP
V
byte data is partially written at the location where
byte write was aborted Block erasure or a repeat of
byte write is required to initialize this data to a
known value
AUTOMATED BLOCK ERASE
As above the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally includ-
ing all preconditioning of block data WSM opera-
tion erase success and V
are monitored and reported through RY BY
the Status Register Additionally if a command other
than Erase Confirm is written to the device following
Erase Setup both the Erase Status and Byte Write
Status bits will be set to ‘‘1’’s When issuing the
Erase Setup and Erase Confirm commands they
should be written to an address within the address
range of the block to be erased Figure 8 shows a
system software flowchart for block erase
Erase typically takes 1 6 seconds per block The
Erase Suspend Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed A system software flowchart is
shown in Figure 9
The entire sequence is performed with V
Abort occurs when RP
falls to V
partially erased by this operation and a repeat of
erase is required to obtain a fully erased block
DESIGN CONSIDERATIONS
Three-Line Output Control
The 28F008SA will often be used in large memory
arrays Intel provides three control inputs to accom-
modate multiple memory connections Three-line
control provides for
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
To efficiently use these control inputs an address
decoder should enable CE
connected to all memory devices and the system’s
READ
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode RP
should be connected to the system Powergood sig-
nal to prevent unintended writes during system pow-
er transitions Powergood should also toggle during
system reset
PP
not occur
drops to V
PPL
control line This assures that only selected
e
2 000 file writes before erase required
while erase is in progress Block data is
PPL
Although the WSM is halted
PP
transitions to V
high voltage presence
while OE
transitions to V
PP
at V
PP
should be
IL
PPH
at V
or V
IL
Byte
PPH
and
PP
or