MB85RC64PNF-G-JNERE1 FUJITSU [Fujitsu Component Limited.], MB85RC64PNF-G-JNERE1 Datasheet - Page 14

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MB85RC64PNF-G-JNERE1

Manufacturer Part Number
MB85RC64PNF-G-JNERE1
Description
Memory FRAM 64 K (8 K x 8) Bit I2C
Manufacturer
FUJITSU [Fujitsu Component Limited.]
Datasheet

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0
MB85RC64
■ POWER ON SEQUENCE
■ NOTES ON USE
14
SDA, SCL level hold time during power down
SDA, SCL level hold time during power up
Power supply rise time
* : SDA, SCL (Max) < V
V
2.7 V
V
1.0 V
V
0 V
• Data written before performing IR reflow is not guaranteed.
• VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may
During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and
A2 pins to “H” or “L”.
CC
IH
IL
SDA, SCL
cause malfunctions, when the power is turned on.
(Max)
(Min)
Parameter
SDA, SCL >V
tpd
CC
+ 0.5 V
CC
× 0.8 *
SDA, SCL : Don't care
Symbol
tpd
tpu
tr
tr
SDA, SCL >V
Min
85
85
10
CC
tpu
Value
× 0.8 *
Max
SDA, SCL
DS05–13109–3E
V
2.7 V
V
1.0 V
V
0 V
CC
IH
IL
Unit
(Max)
(Min)
μs
ns
ns

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