IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet - Page 2

• Manufacturer Part Number: IDT72V205
• Description: 3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
• Manufacturer: IDT [Integrated Device Technology]

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
mable flags is controlled by a simple state machine, and is initiated by asserting
the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used
in a single device configuration.
Standard mode and First Word Fall-Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
There are two possible timing modes of operation with these devices: IDT
In IDT Standard Mode, the first word written to an empty FIFO will not appear
PIN 1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
STQFP (PP64-1, order code: TF)
TQFP (PN64-1, order code: PF)
TOP VIEW
2
TM
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word.
First Word Fall Through mode (FWFT). The XI and XO pins are used to expand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
IDT’s high-speed submicron CMOS technology.
In FWFT mode, the first word written to an empty FIFO is clocked directly
These devices are depth expandable using a Daisy-Chain technique or
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
4294 drw 02
Q
Q
GND
Q
Q
V
Q
Q
Q
Q
Q
Q
Q
V
GND
GND
CC
CC
14
13
12
11
10
9
8
7
6
5
4