IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet - Page 21

• Manufacturer Part Number: IDT72V205
• Description: 3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
NOTES:
1. t
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
D
D
WCLK
Q
RCLK
edge of WCLK and the rising edge of RCLK is less than t
the rising edge of RCLK is less than t
SKEW1
SKEW1
0
WEN
0
0
REN
0
-
-
WCLK
Q
RCLK
OE
D
-
EF
-
WEN
REN
17
17
Q
D
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus t
OR
is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and
17
17
t
ENS
t
DS
t
t
OLZ
Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
ENS
Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing)
W
t
ENH
1
DATA IN OUTPUT REGISTER
t
SKEW1
A
t
REF
t
OE
, then the OR deassertion may be delayed one extra RCLK cycle.
t
DH
FIRST WORD
t
t
t
ENH
t
ENS
DS
SKEW1
1
W
SKEW1
2
t
(1)
. then the EF deassertion may be delayed an extra RCLK cycle.
SKEW1
t
(1)
t
DH
ENH
1
2
W
3
21
LAST WORD
TM
NO OPERATION
3
W
t
t
4
REF
A
t
DS
t
OHZ
2
t
REF
W
t
CLKH
[n +2]
COMMERCIAL AND INDUSTRIAL
t
REF
W
1
TEMPERATURE RANGES
REF
t
CLK
. If the time between the rising
W
t
CLKL
[n+3]
4294 drw 26
4294 drw 27