lxt362 Intel Corporation, lxt362 Datasheet - Page 15

• Manufacturer Part Number: lxt362
• Description: Integrated T1 Lh/sh Transceiver For Ds1/dsx-1 Or Pri Applications
• Manufacturer: Intel Corporation

2.2.2
2.2.3
2.2.4
2.2.5
Datasheet
Figure 3. 50% Duty Cycle Coding
Transmit Monitoring
In Host mode, the Performance Status Register flags open circuits in bit PSR.DFMO. A transition
on DFMO will provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote loopback, Dual loopback, TAOS, or detection
of Network Loop Up code in the receive direction will temporarily disable the high impedance
state.
Transmit Pulse Shape
As shown in
transmitted pulse shape. In Host mode, EC1 through 4 are established by bits 0 through 3 of
Control Register #1 (CR1), respectively. In Hardware mode, pins EC1, EC2, EC3, and EC4 specify
pulse shape.
Shaped pulses meeting the various T1, DS1, and DSX-1 specifications are applied to the AMI line
driver for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1 pulses
for short-haul T1 applications (settings from 0 dB to +6.0 dB of cable), DS1 pulses for long-haul
T1 applications (settings from 0 dB to -22.5 dB). Refer to
specifications.
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362
Table 10 on page
30, Equalizer Control inputs (EC1 through EC4) determine the
Bit Cell
1
0
Figure 14 on page 40
Figure
1
3. To reduce power
for pulse mask
15