ST16C2552CJ44 EXAR [Exar Corporation], ST16C2552CJ44 Datasheet - Page 11

• Manufacturer Part Number: ST16C2552CJ44
• Description: 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

REV. 4.2.1
Table 5
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.10
2.10.1
2.10.2
O
UTPUT
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
Transmitter
shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
400
Data Rate
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
T
ABLE
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
5: T
Clock (Decimal)
D
IVISOR FOR
YPICAL DATA RATES WITH A
2304
384
192
96
48
24
12
6
4
2
1
16x
D
IVISOR FOR
Clock (HEX)
900
180
C0
0C
60
30
18
06
04
02
01
16x
14.7456 MH
11
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
DLM P
V
ALUE
Z CRYSTAL OR EXTERNAL CLOCK
09
01
00
00
00
00
00
00
00
00
00
ROGRAM
(HEX)
DLL P
V
ALUE
C0
0C
00
80
60
30
18
06
04
02
01
ROGRAM
(HEX)
ST16C2552
D
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)