ST16C2552CJ44 EXAR [Exar Corporation], ST16C2552CJ44 Datasheet - Page 36

• Manufacturer Part Number: ST16C2552CJ44
• Description: 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ABSOLUTE MAXIMUM RATINGS...................................................................................26
ELECTRICAL CHARACTERISTICS ................................................................................26
PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................33
TABLE OF CONTENTS ................................................................................................................................. I
T
T
F
F
F
F
F
F
F
F
F
F
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
4.8 M
4.9 L
4.10 M
4.11 S
4.12 B
4.13 A
DC E
AC E
10: P
11: UART RESET CONDITIONS FOR CHANNEL A AND B ................................................................................................... 25
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.97 to 5.5V............................................ 27
70 pF load where applicable .............................................................................................................................. 27
12. C
13. M
14. D
15. D
17. T
16. R
18. R
19. R
20. T
21. T
INE
LECTRICAL
LECTRICAL
ODEM
CRATCH
AUD
LTERNATE
ODEM
ARITY SELECTION
S
RANSMIT
RANSMIT
RANSMIT
LOCK
ATA
ATA
ECEIVE
ECEIVE
ECEIVE
ODEM
TATUS
R
C
B
B
ATE
S
ONTROL
T
US
US
I
TATUS
IMING
NPUT
P
R
R
R
R
R
R
C
C
R
W
EADY AND
EADY
EADY
AD
F
R
G
EADY
EADY
EADY
EAD
HARACTERISTICS
HARACTERISTICS
RITE
UNCTION
EGISTER
/O
ENERATOR
.................................................................................................................................................................... 28
R
UTPUT
& I
& I
T
................................................................................................................................................................ 21
R
EGISTER
T
& I
& I
& I
R
IMING
IMING
EGISTER
NTERRUPT
NTERRUPT
EGISTER
NTERRUPT
NTERRUPT
NTERRUPT
I
NTERRUPT
T
..................................................................................................................................................... 29
IMING
R
(LSR) - R
.................................................................................................................................................... 29
EGISTER
R
(SPR) - R
EGISTERS
T
T
(MSR) - R
F
(MCR)
T
T
T
IMING
IMING
OR
T
IMING
IMING
IMING
............................................................................................................27
...........................................................................................................26
IMING
C
EAD
HANNELS
[FIFO M
[FIFO M
(AFR) - R
[N
[FIFO M
[FIFO M
[N
OR
EAD
ON
ON
(DLL
O
EAD
-FIFO M
G
NLY
-FIFO M
/W
ODE
ODE
A & B......................................................................................................... 28
ENERAL
ODE
ODE
O
RITE
AND
, DMA D
, DMA E
EAD
..................................................................................... 22
NLY
, DMA M
, DMA M
ODE
ODE
II
/W
DLM) - R
............................................................................... 24
]
P
............................................................................. 23
]
FOR
RITE
NABLED
URPOSE
FOR
ISABLED
ODE
ODE
C
C
HANNELS
D
E
HANNELS
................................................................... 24
]
NABLED
]
ISABLED
EAD
FOR
FOR
O
UTPUTS
/W
C
C
A & B ............................................................... 30
HANNELS
]
HANNELS
]
A & B ............................................................. 30
RITE
FOR
FOR
C
C
............................................... 24
HANNELS
C
HANNELS
A & B ................................................ 31
A & B ............................................... 31
ONTROL
A & B.................................... 32
A & B ................................... 32
- R
EAD
/W
RITE
........ 21
REV. 4.2.1