alc272 Realtek Semiconductor Corporation, alc272 Datasheet - Page 27

• Manufacturer Part Number: alc272
• Description: 4 Channel High Definition Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

Exit from ‘Link Reset’:
100µsec provides time for the codec PLL to stabilize)
bit of frame SYNC)
7.3.2.
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
In the ALC272, the extend power state of conforming to Intel low power ECR the function reset could
not initialize the register setting. Host SW needs to send “two” function reset consecutively to reset all
settings.
4 Channel High Definition Audio Codec
BCLK
SYNC
SDOs
SDIs
RST#
If BCLK is re-started for any reason (codec, wake-up event, power management, etc.)
Minimum of 4 BCLKs after RESET# is de-asserted, the controller starts to signal normal frame SYNC
The codec drives its SDI to request an initialization sequence (when the SDI is driven high at the last
Software is responsible for de-asserting RESET# after a minimum of 100µs BCLK running time (the
Codec Reset
1
2
Previous Frame
SYNC is absent
Normal Frame
3
Driven Low
Driven Low
Driven Low
4 BCLK
Figure 12. Link Reset Timing
4
4 BCLK
19
5
Pulled Low
Pulled Low
Pulled Low
Pulled Low
Link in Reset
6
>=100 usec
Track ID: JATR-1076-21
7
>= 4 BCLK
Wake Event
8
Initialization Sequence
Normal Frame
SYNC
Datasheet
ALC272
9
Rev. 1.0