alc250-lf Realtek Semiconductor Corporation, alc250-lf Datasheet - Page 20

• Manufacturer Part Number: alc250-lf
• Description: Two-channel Ac?97 2.3 Audio Codec With Equalizer
• Manufacturer: Realtek Semiconductor Corporation

6.1.19 MX28 Extended Audio ID
Default: 0605h
The Extended Audio ID register is a read only register used to communicate information to the digital controller on two functions.
ALC250 is designed as the primary CODEC with ID is ‘00’.
6.1.20 MX2A Extended Audio Status and Control
Default: 0000h
This register contains two active bits for powerdown and status of the surrounding DACs. Bits 0, 1 & 2 are read/write bits which
are used to enable or disable VRA, DRA and SPDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK
slot assignment of the S/PDIF. Bit 10 is a read only bit which tells the controller if the S/PDIF configuration is valid.
Two-Channel AC’97 2.3 Audio Codec
15:14
13:12
11:10
14:11
Bit
8:6
5:4
Bit
9:6
5:4
15
10
9
3
2
1
0
3
2
1
0
The ALC250 maps DAC slot according to the following table: (default maps to AC’97 spec. rev2.3)
sampling rate defined in MX2C and MX32. VRA also control write operation of MX2Cand MX32.
If VRA = 0, ALC250 ADC/DAC operate at fixed 48KHz sampling rate. Otherwise, it operates with variable
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
NA
R
R
R
R
R
R
R
DSA[1:0]
ID[1:0], read as ‘00’.
Reserved, Read as 0
REV[1:0]=10 to indicate that the ALC250 is AC’97 rev2.3 compliant
AMAP read as 1 (DAC mapping based on ID)
Reserved, Read as 0
DAC Slot Assignment DSA[1:0] (Default value depends on ID[1:0])
DSA[1:0] Controls the DAC slot assignment, as described in AC’97 rev2.2.
Reserved, Read as 0
SPDIF Read as 1 (S/PDIF is supported)
DRA Read as 1
VRA Read as 1 (Variable Rate Audio is supported)
Validity Configuration of S/PDIF Output (VCFG)
Reserved
S/PDIF Configuration Valid (SPCV)
Reserved
SPSA[1:0], S/PDIF Slot Assignment when DRS=0
SPSA[1:0], S/PDIF-Out Slot Assignment when DRS=1(for 96K S/PDIF-Out)
Reserved
SPDIF 1: Enable 0: Disable (SPDIFO is in high impedance)
DRA
VRA
Combines with MX3A.15 to decide validity control in S/PDIF output signal.
0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.
1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid.
00: S/PDIF source data assigned to AC-LINK slot3/4
01: S/PDIF source data assigned to AC-LINK slot7/8 (Default when ID=00)
10: S/PDIF source data assigned to AC-LINK slot6/9 (Default when ID=01,10)
11: S/PDIF source data assigned to AC-LINK slot10/11 (Default when ID=11)
01: S/PDIF-Out source is from AC-LINK slot3/4 + slot7/8.
0,0
0,1
1,0
1,1
1: Enable 0: Disable
1: Enable 0: Disable
Left DAC slot #
10
3
7
6
Right DAC slot #
15
11
4
8
9
Function
Function
Default when ID[1:0]=00
Default when ID[1:0]=01,10
Default when ID[1:0]=11
Comment
-
ALC250 DataSheet
Rev1.3