alc888-vc2-gr Realtek Semiconductor Corporation, alc888-vc2-gr Datasheet - Page 19

• Manufacturer Part Number: alc888-vc2-gr
• Description: 7.1+2 Channel High Definition Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

7.1.1.
7.1+2 Channel High Definition Audio Codec
Item
BCLK
SYNC
SDO
SDI
RST#
Signal Name
BCLK
SYNC
SDO
SDI
RST#
SYNC
BCLK
SDO
SDI
Signal Definitions
Description
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are
carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec
samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at
least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.
Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be
supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each
rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Codec/Controller
Controller
Controller
Controller
Controller
Source
Controller samples SDI at rising edge of BCLK
Type for Controller
Codec samples SDO at both rising and falling edge of BCLK
8-Bit Frame SYNC
Table 6.
Table 5.
Input/Output
7
3
Output
Output
Output
Output
6
5
Figure 5.
2
4
HDA Signal Definitions
3
Link Signal Definitions
1
2
11
1
0
Description
Global 24.0MHz Bit Clock
Global 48kHz Frame Sync and Outbound Tag Signal
Serial Data Output from Controller
Serial data input from codec. Weakly pulled down by the
controller
Global Active Low Reset Signal
Bit Timing
0
999 998 997 996 995 994 993 992 991 990
499
Start of Frame
498
497
496
Track ID: JATR-1076-21
495
494
Datasheet
ALC888
Rev. 1.4