mu9c4485a Music Semiconductors, Inc., mu9c4485a Datasheet
mu9c4485a
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mu9c4485a Summary of contents
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APPLICATION BENEFITS Enhances Ethernet and Token-Ring LAN bridges and switches: Ø 64-bit width stores 48-bit MAC address plus associated data (Port ID, time stamp, “permanent” flag) Ø 32-bit I/O supports multiple ports of fast (100 Mb) Ethernet or Gigabit Ethernet ...
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... WidePort LANCAM ® The MU9C4485A/L, MU9C2485A/L, and MU9C1485A/L WidePort LANCAMs are 64-bit wide content-addressable memories (CAMs), featuring a 32-bit wide interface. This interface doubles the available I/O bandwidth in many applications while maintaining the same powerful enhanced architecture and instruction set as the MU9C2480A/L. Content-addressable memories, also known as associative memories, operate in the converse way to random access memories (RAM) ...
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All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of ...
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WidePort LANCAM ® /RESET (Reset, Input, TTL) /RESET must be driven LOW to place the device in a known state before operation, which will reset the device to the conditions shown in Table 5. The /RESET pin should be driven ...
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FUNCTIONAL DESCRIPTION Continued Each entry has two validity bits (known as Skip bit and Empty bit) associated with it to define its particular type: empty, valid, skip, or RAM. When data is written to the active Comparand register, and the ...
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WidePort LANCAM ® FUNCTIONAL DESCRIPTION Continued address of the Highest-Priority Matching location in that device, concatenated with its page address, along with flags indicating internal match, multiple match, and full. When the Status register is read with a Command Read ...
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Throughout the following, “aaaH” represents a three- digit hexadecimal number “aaa,” while “bbB” represents a two-digit binary number “bb.” All memory locations are written to or read from in 32-bit segments. Segment 0 corresponds to the lowest order bits (bits ...
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WidePort LANCAM ® OPERATIONAL CHARACTERISTICS Continued Cycle Type /E /CM /W I/O Status Cmd Write Cmd Read OUT OUT OUT OUT OUT OUT OUT OUT HIGH-Z Data Write Data Read L ...
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OPERATIONAL CHARACTERISTICS Continued CAM Status Validity bits at all memory locations Match and Full flag outputs IEEE 802.3-802.5 Input Translation CAM/RAM Partitioning Comparison Masking Address register auto-increment or -decrement Source and Destination Segment counters count ranges Address register and Next ...
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WidePort LANCAM ® OPERATIONAL CHARACTERISTICS Continued in Enhanced mode not necessary to unlock the daisy chain with a NOP instruction before command or data writes after a non-matching compare, as required in Standard mode. Segment Control Register (SC) ...
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OPERATIONAL CHARACTERISTICS Continued Case Internal Internal /EC(int) /MA (int Case Internal Internal /EC(int) /MA (int ...
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WidePort LANCAM ® OPERATIONAL CHARACTERISTICS Continued instructions. During an automatic or forced compare, the Comparand register is simultaneously compared against the CAM portion of all memory locations with the correct validity condition. Automatic compares always compare against valid memory locations, ...
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OPERATIONAL CHARACTERISTICS Continued / 5– / – /CM /W DQ3 1 – the Comparand Write ...
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WidePort LANCAM ® OPERATIONAL CHARACTERISTICS Continued /E /EC /EC (INT ) /MF Figure 6: /EC(Int) Timing Diagram COMPARE OPERATIONS During a Compare operation, the data in the Comparand register is compared to all locations in the Memory array simultaneously. Any ...
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OPERATIONAL CHARACTERISTICS Continued Table 6a (Standard mode) and Table 6b (Enhanced mode) show when a device will respond to reads or writes and when it will not, based on the state of /EC(int), the internal match condition, and other control ...
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WidePort LANCAM ® OPERATIONAL CHARACTERISTICS Continued Setting Page Address Register Values In a vertically cascaded system, the user must set the individual Page Address registers to unique values by using the Page Address initialization mechanism. Each Page Address register must ...
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Instruction: Select Persistent Source (SPS) Binary Op-Code: 0000 f000 0000 0sss* f Address Field flag† sss Selected source This instruction selects a persistent source for data reads, until another SPS instruction changes reset occurs. The default source ...
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WidePort LANCAM ® INSTRUCTION SET DESCRIPTIONS Continued Instruction: Compare (CMP) Binary Op-Code: 0000 0101 0000 0vvv* vvv Validity condition A CMP instruction forces a Comparison of Valid, Skipped, or Random entries against the Comparand register through ...
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MNEMONIC FORMAT INS dst,src[msk],val INS: Instruction mnemonic dst: Destination of the data src: Source of the data msk: Mask register used val: Validity condition set at the location written Instruction: Select Persistent Source Operation Mnemonic Comparand Register SPS CR Mask ...
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WidePort LANCAM ® INSTRUCTION SET SUMMARY Continued Instruction: Data Move Continued Operation Mnemonic Mask Register 1 from: Comparand Register MOV MR1,CR No Operation NOP Mask Register 2 MOV MR1,MR2 Memory at Address Reg. MOV MR1,[AR] Memory at Address MOV MR1,aaaH ...
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INSTRUCTION SET SUMMARY Continued CYCLE LENGTH Command Write MOV reg, reg (except L-70) Short TCO reg (except CT) TCO CT (non-reset, HMA invalid) SPS, SPD, SFR SBR, RSC, NOP ) SFT (A MOV reg, reg (L-70) Medium MOV reg, mem ...
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WidePort LANCAM ® REGISTER BIT ASSIGNMENTS Continued 31 30 4485A/L /MA /MM /MA 2485A/L /MM /MA /MM 1485A 4485A/L Page Address, PA3–0 2485A/L Page Address, PA4–0 1485A/L Page Address, PA5–0 Note: The Next Free Address register is read ...
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Supply Voltage “A” Devices “L” Devices Voltage on all other pins Temperature under bias Storage Temperature DC Output Current OPERATING CONDITIONS (voltages referenced to GND at the device pin) Symbol Parameter V CC Operating Supply Voltage V IH Input Voltage ...
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WidePort LANCAM ® OPERATIONAL CHARACTERISTICS Continued Symbol Parameter C IN Input Capacitance C OUT Output Capacitance Input Signal Transitions Input Signal Rise Time Input Signal Fall Time Input Timing Reference Level Output Timing Reference Level ...
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OPERATIONAL CHARACTERISTICS Continued SWITCHING CHARACTERISTICS (see Note 3) · Available N/A Not Available No Symbol Parameter (all times in nanoseconds) t ELEL 1 Chip Enable Compare Cycle Time t ELEH 2 Chip Enable LOW Pulse Width t EHEL 3 Chip ...
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WidePort LANCAM ® READ CYCLE – Rev. 2 Family TIMING DIAGRAMS 3 8 ...
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Dim. A1 Dim. A2 80-pin 0.05 1.35 TQFP 0.15 1.45 PACKAGE OUTLINE Dim. b Dim. c Dim. D Dim. E 0.22 0.08 13.90 13.90 0.38 0.20 14.10 14.10 27 ...
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... MU9C4485A - 12TCC 4096 x 64 MU9C4485L - 70TCC 4096 x 64 MU9C4485L - 90TCC 4096 x 64 MU9C4485L - 12TCC 4096 x 64 MU9C4485A - 70TCI 4096 x 64 MU9C4485A - 90TCI 4096 x 64 MU9C4485A - 12TCI 4096 x 64 MU9C2485A - 50TCC 2048 x 64 MU9C2485A - 70TCC 2048 x 64 MU9C2485A - 90TCC 2048 x 64 MU9C2485A - 12TCC ...