mu9c4485a Music Semiconductors, Inc., mu9c4485a Datasheet - Page 18

• Manufacturer Part Number: mu9c4485a
• Description: Wideport Lancam? Family
• Manufacturer: Music Semiconductors, Inc.

WidePort LANCAM
Instruction: Compare (CMP)
Binary Op-Code: 0000 0101 0000 0vvv*
A CMP V, S, or R instruction forces a Comparison of Valid,
Skipped, or Random entries against the Comparand register
through a mask register, if one is selected. During a CMP E
instruction, the compare is only done on the Validity bits
and all data bits are automatically masked.
Instruction: Special Instructions
Binary Op-Code: 0000 0110 00dd drrr*
These instructions are a special set for the A/L WidePort
LANCAMs to accommodate the added features over the
MU9C1485. Two alternate sets of configuration registers
can be selected by using the Select Foreground and Select
Background Registers instructions. These registers are the
Control, Segment Control, Address, Mask Register 1, and
the PS and PD registers. An RSC instruction resets the
Segment Control register count values for both the
Destination and Source counters to the original Start limits.
The Shift instructions shift the designated register one bit
right or left. The right and left limits for shifting are
determined by the CAM/RAM partitioning set in the Control
register. The Comparand register is a barrel-shifter, and for
the example of a device set to 64 bits of CAM executing a
Shift Comparand Right instruction, bit 0 is moved to bit 63,
bit 1 is moved to bit 0, and bit 63 is moved to bit 62. For a
Shift Comparand Left instruction, bit 63 is moved to bit 0,
bit 0 is moved to bit 1, and bit 62 is moved to bit 63. MR2
acts as a sliding mask, where for a Shift Right instruction
bit 1 is moved to bit 0, while bit 0 “falls off the end,” and bit
63 is replicated to bit 62. For a Shift Mask Left instruction,
bit 0 is replicated to bit 1, bit 62 is moved to bit 63, and bit 63
"falls off the end.” With shorter width CAM fields, the
bit limits on the right or left move to match the width of
CAM field.
Rev. 2
rrr
ddd
vvv
Validity condition
Target resource
Operation
INSTRUCTION SET DESCRIPTIONS Continued
®
Family
18
Instruction: Set Full Flag (SFF)
Binary Op-Code: 0000 0111 0000 0000*
The SFF instruction is a special instruction used to force
the Full flag LOW to permit setting the Page Address
register in vertically cascaded systems.
Instruction: No Operation (NOP)
Binary Op-Code: 0000 0011 0000 0000
The NOP (No-OP) belongs to the MOV instructions, where
a register is moved to itself. No change occurs within the
device. This instruction is useful in unlocking the daisy
chain in Standard mode.
Notes:
§ Instruction cycle lengths given in Table 8.
* Instruction Op-Codes are loaded on the DQ31–16 lines.
† If f=1, the instruction requires an absolute address
(or register contents for TCOs) to be supplied onthe
DQ15–0 lines. Supplied addresses will update the
Address register to the “aaaH” value supplied. After
an operation involving M@[AR] or M@aaaH, the
Address register will be incremented or decremented
depending on the setting in the Control register.