DS24B33+ MAXIM [Maxim Integrated Products], DS24B33+ Datasheet - Page 19

• Manufacturer Part Number: DS24B33+
• Description: 4Kb 1-Wire EEPROM with 200k Write/Erase Cycles
• Manufacturer: MAXIM [Maxim Integrated Products]

A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V
until the read low time t
dow, when responding with a 0, the DS24B33 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS24B33 does not hold the data line low at all, and the
voltage starts rising as soon as t
The sum of t
nal timing generator of the DS24B33 on the other side
define the master sampling window (t
t
the data line. For the most reliable communication, t
should be as short as permissible, and the master
should read close to but no later than t
reading from the data line, the master must wait until
t
time t
slot. Note that t
single DS24B33 attached to a 1-Wire line. For multide-
vice configurations, t
accommodate the additional 1-Wire device input
capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as
the DS2482-x00 or DS2480B 1-Wire line drivers can be
used.
In a 1-Wire environment, line termination is possible
only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are suscep-
tible to noise of various origins. Depending on the phys-
ical size and topology of the network, reflections from
end points and branch points can add up or cancel
each other to some extent. Such reflections are visible
as glitches or ringing on the 1-Wire communication line.
Figure 12. Hysteresis at the Low-to-High Switching Threshold
MSRMAX
SLOT
REC
is expired. This guarantees sufficient recovery
) in which the master must perform a read from
V
for the DS24B33 to get ready for the next time
PUP
V
Improved Network Behavior
TH
0V
RL
V
+ δ (rise time) on one side and the inter-
HY
REC
(Switchpoint Hysteresis)
______________________________________________________________________________________
specified herein applies only to a
RL
REC
is expired. During the t
needs to be extended to
RL
is over.
Slave-to-Master
MSRMAX
MSRMIN
RL
. After
win-
RL
TL
to
4Kb 1-Wire EEPROM with
200k Write/Erase Cycles
Noise coupled onto the 1-Wire line from external
sources can also result in signal glitching. A glitch dur-
ing the rising edge of a time slot can cause a slave
device to lose synchronization with the master and,
consequently, result in a Search ROM command com-
ing to a dead end or cause a device-specific function
command to abort. For better performance in network
applications, the DS24B33 uses an improved 1-Wire
front-end, which makes it less sensitive to noise.
The 1-Wire front-end of the DS24B33 differs from tradi-
tional slave devices in one characteristic: There is a hys-
teresis at the low-to-high switching threshold V
negative glitch crosses V
V
is effective at any 1-Wire speed.
The DS24B33 uses two different types of CRCs. One
CRC is an 8-bit type and is stored in the most signifi-
cant byte of the 64-bit registration number. The bus
master can compute a CRC value from the first 56 bits
of the 64-bit registration number and compare it to the
value stored within the DS24B33 to determine if the reg-
istration number has been received error-free. The
equivalent polynomial function of this CRC is X
X
ed) form. It is computed and programmed into the chip
at the factory.
The other CRC is a 16-bit type, generated according to
the standardized CRC-16 polynomial function X
+ X
transfer when writing to the scratchpad. In contrast to
the 8-bit CRC, the 16-bit CRC is always communicated
in the inverted form. A CRC generator inside the
DS24B33 (Figure 13) calculates a new 16-bit CRC, as
shown in the command flowchart (Figure 7). The bus
master compares the CRC value read from the device
to the one it calculates from the data, and decides
whether to continue with an operation.
With the Write Scratchpad command, the CRC is gen-
erated by first clearing the CRC generator and then
shifting in the command code, the target addresses
TA1 and TA2, and all the data bytes as they were sent
by the bus master. The DS24B33 transmits this CRC
only if the data bytes written to the scratchpad include
scratchpad ending offset 11111b. The data can start at
any location within the scratchpad.
For more information on generating CRC values refer to
Application Note 27: Understanding and Using Cyclic
Redundancy Checks with Maxim iButton Products .
TH
4
+ 1. This 8-bit CRC is received in the true (noninvert-
2
- V
+ 1. This CRC is used for fast verification of a data
HY
, it is not recognized (Figure 12). The hysteresis
TH
CRC Generation
but does not go below
8
16
TH
+ X
+ X
. If a
5
19
15
+