DS90CR283MTD NSC [National Semiconductor], DS90CR283MTD Datasheet
DS90CR283MTD
Related parts for DS90CR283MTD
DS90CR283MTD Summary of contents
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... With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable Block Diagrams DS90CR283 Order Number DS90CR283MTD See NS Package Number MTD56 TRI-STATE ® registered trademark of National Semiconductor Corporation. ...
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Pin Diagrams DS90CR283 Typical Application www.national.com DS90CR284 DS012889-21 2 DS012889-22 DS012889-23 ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Ouput Voltage −0. LVDS Receiver ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter RECEIVER SUPPLY CURRENT I Receiver Supply Current, CCRW Worst Case I Receiver Supply Current, CCRZ Power Down Note 1: “Absolute Maximum Ratings” are those values beyond ...
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Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time ( Figure 3 ) CMOS/TTL High-to-Low Transition Time ( Figure 3 ) CHLT RSKM RxIN Skew Margin (Note 7), = ...
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AC Timing Diagrams (Continued) FIGURE 4. DS90CR283 (Transmitter) Input Clock Transition Time = 0V Note 8: Measurements at V diff Note 9: TCCS measured between earliest and latest initial LVDS edges. Note 10: TxCLK OUT Differential Low High Edge FIGURE ...
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AC Timing Diagrams (Continued) FIGURE 8. DS90CR283 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90CR284 (Receiver) Clock In to Clock Out Delay FIGURE 10. DS90CR283 (Transmitter) Phase Lock Loop Set Time FIGURE 11. DS90CR284 (Receiver) Phase Lock Loop ...
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AC Timing Diagrams (Continued) FIGURE 12. Seven Bits of LVDS in One Clock Cycle FIGURE 13. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR283) www.national.com FIGURE 14. Transmitter Powerdown Delay FIGURE 15. Receiver Powerdown Delay 8 DS012889-15 DS012889-16 ...
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AC Timing Diagrams (Continued) FIGURE 16. Transmitter LVDS Output Pulse Position Measurement SW — Setup and Hold Time (Internal data sampling window) TCCS — Transmitter Output Skew RSKM Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) Cable ...
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DS90CR283 Pin Description — Channel Link Transmitter Pin Name I/O No. TxIN I 28 TTL Level inputs TxOUT Positive LVDS differential data output TxOUT− Negative LVDS differential data output TxCLK TTL level clock ...
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Applications Information (Continued) plications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally per- form well in short point-to-point applications while Twin-Coax is ...
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Applications Information FIGURE 19. CHANNEL LINK Decoupling Configuration CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CR283MTD or DS90CR284MTD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION ...