DS90CR283MTD NSC [National Semiconductor], DS90CR283MTD Datasheet - Page 5

• Manufacturer Part Number: DS90CR283MTD
• Description: 28-Bit Channel Link-66 MHz
• Manufacturer: NSC [National Semiconductor]

CLHT
CHLT
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Receiver Switching Characteristics
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM
Over recommended operating supply and temperature ranges unless otherwise specified
AC Timing Diagrams
Symbol
cable skew (type, length) + source clock jitter (cycle to cycle)
CMOS/TTL Low-to-High Transition Time ( Figure 3 )
CMOS/TTL High-to-Low Transition Time ( Figure 3 )
RxIN Skew Margin (Note 7),
V
RxCLK OUT Period ( Figure 7 )
RxCLK OUT High Time ( Figure 7 )
RxCLK OUT Low Time ( Figure 7 )
RxOUT Setup to RxCLK OUT ( Figure 7 )
RxOUT Hold to RxCLK OUT ( Figure 7 )
RxCLK IN to RxCLK OUT Delay
V
Receiver Phase Lock Loop Set ( Figure 11 )
Receiver Power Down Delay ( Figure 11 )
CC
CC
= 5V, T
= 5.0V ( Figure 9 )
FIGURE 3. DS90CR284 (Receiver) CMOS/TTL Output Load and Transition Timing
FIGURE 2. DS90CR283 (Transmitter) LVDS Output Load and Transition Timing
DS012889-3
A
= 25˚C ( Figure 17 )
DS012889-5
Parameter
FIGURE 1. “WORST CASE” Test Pattern
@
25˚C,
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
5
10.5
Min
700
600
4.3
7.0
4.5
2.5
6.5
6.4
15
6
4
Typ
2.5
2.0
4.2
5.2
T
5
9
Max
10.7
DS012889-2
4.0
4.0
50
10
1
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DS012889-4
DS012889-6
Units
ms
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs