CY2412-1 CYPRESS [Cypress Semiconductor], CY2412-1 Datasheet

CY2412-1

Manufacturer Part Number

CY2412-1

Description

MPEG Clock Generator with VCXO

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY2412-1.pdf (6 pages)

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Cypress Semiconductor Corporation

Document #: 38-07227 Rev. *D

Features

13.5 XIN

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V operation

• 8-pin SOIC package

Logic Block Diagram

Part Number

XOUT

VCXO

CY2412-1

CY2412-3

OSC

Outputs

13.5-MHz pullable crystal input per

Cypress specification

13.5-MHz pullable crystal input per

Cypress specification

Input Frequency Range

PLL

VCO

VDD

•

VSS

3901 North First Street

MPEG Clock Generator with VCXO

DIVIDERS

OUTPUT

Benefits

• Highest-performance PLL tailored for multimedia appli-

• Meets critical timing requirements in complex system

• Large ± 150-ppm range, better linearity

• Enables application compatibility

Two 27 MHz outputs, one 54 MHz (3.3V) Linear

27 MHz, 13.5 MHz, 54 MHz (3.3V)

cations

designs

•

Output Frequencies

CLKC

CLKB

CLKA

San Jose

CA 95134

Revised December 13, 2004

Pin Configuration

VCXO

VSS

XIN

VDD

CY2412-1,-3

8-pin SOIC

•

Linear

VCXO Profile

408-943-2600

CY2412

CLKC

CLKB

CLKA

XOUT

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