PS10 SUTEX [Supertex, Inc], PS10 Datasheet - Page 3

• Manufacturer Part Number: PS10
• Description: Quad Power Sequencing Controller
• Manufacturer: SUTEX [Supertex, Inc]

PWRGD Logic
Pinout
Pin Description
PWRGD-D – This open drain Power Good Output Pin is
held inactive on initial power application and goes active a
programmed time delay after PWRGD-C goes active.
PWRGD-C – This open drain Power Good Output Pin is
held inactive on initial power application and goes active a
programmed time delay after PWRGD-B goes active.
PWRGD-B – This open drain Power Good Output Pin is
held inactive on initial power application and goes active a
programmed time delay after PWRGD-A goes active.
PWRGD-A – This open drain Power Good Output Pin is
held inactive on initial power application and goes active one
POR delay after the UV pin goes above its High threshold
(provided V
period).
To function as an indicator a pullup resistor must be con-
nected from this pin to a voltage rail no more than 90V from
V
OV – This Over Voltage (OV) sense pin, when raised above
its high threshold will immediately cause the Power Good
Outputs to be pulled low. These outputs will remain low until
the voltage on this pin falls below the low threshold limit,
initiating a new start-up cycle.
UV – This Under Voltage (UV) sense pin, when lowered
below its low threshold will immediately cause the Power
Good Outputs to be pulled low. These outputs will remain
low until the voltage on this pin rises above the low thresh-
old limit, initiating a new start-up cycle.
EE
.
Model
PS10
PS11
PWRGD-D (PS10)
PWRGD-D (PS11)
PWRGD-C (PS10)
PWRGD-C (PS11)
PWRGD-B (PS10)
PWRGD-B (PS11)
PWRGD-A (PS10)
PWRGD-A (PS11)
IN
stays within the UV/OV window during this
INACTIVE (not ready)
INACTIVE (not ready)
ACTIVE (Ready)
ACTIVE (Ready)
OV
UV
V
Condition
EE
1
2
3
4
5
6
7
Top View
PWRGD-A/B/C/D
0
1
1
0
14
13
12
11
10
9
8
TD
V
TC
NC
RAMP
TB
NC
IN
HI Z
HI Z
V
V
EE
EE
V
input to the circuit.
V
input to the circuit and can withstand 90V with respect to
V
TD – The resistor connected from this pin to V
time delay from PWRGD-C going active to PWRGD-D going
active.
TC – The resistor connected from this pin to V
time delay from PWRGD-B going active to PWRGD-C going
active.
TB – The resistor connected from this pin to V
time delay from PWRGD-A going active to PWRGD-B going
active.
RAMP – This pin provides a current output so that a timing
ramp is generated when a capacitor is connected. This tim-
ing Ramp is used to program POR and the time from satis-
faction of the UV/OV supervisors to PWRGD-A.
NC– No Connect. This pin can be grounded or left floating.
3
EE
IN
EE
.
– This pin is the positive terminal of the power supply
- This pin is the negative terminal of the power supply
EE
EE
EE
pin sets the
pin sets the
pin sets the
A051204