LT1236A-5 LINER [Linear Technology], LT1236A-5 Datasheet - Page 11

• Manufacturer Part Number: LT1236A-5
• Description: Easy-to-Use, Ultra-Tiny 16-Bit ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Examples of Aborting Cycle using CS
For some applications the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2450-1 is in
the data output state, a CS rising edge clears the remaining
data bits from memory, aborts the output cycle and triggers
a new conversion. Figure 9 shows an example of aborting
an I/O with idle-high (CPOL = 1) and Figure 10 shows an
example of aborting an I/O with idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 11. If SCK is maintained at a LOW
logic level, after the end of a conversion cycle, a new
SD0
SCK
CS
CS
SD0
SCK
Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
CONVERT
CONVERT
Figure 7. Idle-Low (CPOL = 0) Clock. ⎯ C ⎯ S Triggers a New Conversion
LOW I
LOW I
SLEEP
SLEEP
CC
CC
D
clk
D
clk
15
15
1
1
D
clk
D
clk
14
14
2
2
conversion operation can be triggered by pulling CS low
and then high. When CS is pulled low (CS = LOW), SDO
will output the most signifi cant bit (D15) of the result of
the just completed conversion. While a low logic level is
maintained at SCK pin and CS is subsequently pulled high
(CS = HIGH) the remaining 15 bits of the result (D14:D0)
are discarded and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively infl uence
the conversion accuracy.
D
clk
D
13
clk
13
DATA OUTPUT
3
DATA OUTPUT
3
D
D
clk
12
clk
12
4
4
clk
clk
D
14
D
2
2
14
clk
D
clk
D
1
15
1
15
clk
D
D
16
0
clk
0
16
CONVERT
CONVERT
LTC2450-1
24501 F07
24501 F08
11
24501fb