LT1236A-5 LINER [Linear Technology], LT1236A-5 Datasheet - Page 16

• Manufacturer Part Number: LT1236A-5
• Description: Easy-to-Use, Ultra-Tiny 16-Bit ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2450-1
For most applications, it is desirable to implement C
a high quality 0.1μF ceramic capacitor and R
capacitor should be located as close as possible to the
actual V
by this circuit path as well as the path length should be
minimized.
In the case of a 2-wire sensor which is not remotely
grounded, it is desirable to split R
resistors in the ADC input line as well as in the sensor
ground return line which should be tied to the ADC GND
pin using a star connection topology.
Figure 16 shows the measured LTC2450-1 INL vs
Input Voltage as a function of R
capacitor C
In some cases, R
lines. The input current is zero while the ADC is either in
sleep or I/O modes. Thus, if the time constant of the input
R-C circuit τ = R
16
IN
Figure 16. Measured INL vs Input Voltage,
C
package pin. Furthermore the area encompassed
–12
–16
IN
12
–4
–8
16
IN
8
4
0
= 0.1μF , V
0
= 0.1μF .
S
S
• C
1
can be increased above these guide-
IN
CC
INPUT VOLTAGE (V)
is of the same order magnitude or
= 5V, T
2
R
R
S
S
= 10k
= 1k
A
= 25°C
3
R
S
S
= 0
value with an input
4
S
and place series
24501 F16
5
S
≤ 1k. This
IN
as
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≅ 1/(2π • R
Finally, if the recommended choice for C
for the user’s specifi c application, an alternate strategy is to
eliminate C
this confi guration corresponds to a low impedance sensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measure-
ments, low impedance voltage source monitoring and so
on. The resultant INL vs V
measurements of Figure 17 include a C
responding to a minimum size layout pad and a minimum
width input trace of about 1 inch length.
Figure 17. Measured INL vs V
IN
–2
–4
–6
–8
8
6
4
2
0
and minimize C
0
R
S
0.5
= 0
1
R
S
R
1.5
= 10k
S
INPUT VOLTAGE (V)
= 1k
2
IN
PAR
2.5
IN
is shown in Figure 17. The
, C
3
and R
IN
3.5
= 0, V
S
4
. In practical terms,
IN
PAR
CC
4.5
24501 F17
is unacceptable
= 5V, T
capacitor cor-
5
A
S
= 25°C
• C
24501fb
IN
).