X1227 Xicor, X1227 Datasheet - Page 12

• Manufacturer Part Number: X1227
• Description: Real Time Clock/Calendar/CPU Supervisor with EEPROM
• Manufacturer: Xicor

Figure 10. Slave Address, Word Address, and Data Bytes (64 Byte pages)
X1227
Figure 11. Byte Write Sequence
Figure 12. Writing 30 bytes to a 64-byte memory page starting at address 40.
REV 1.1.20 1/13/03
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
Array
CCR
7 Bytes
Signals from
the Master
SDA Bus
Signals From
The Slave
A7
1
1
D7
0
Address
= 6
Device Identifier
0
1
A6
D6
0
A5
D5
1
0
0
Address Pointer
Ends Here
Addr = 7
S
a
r
t
t
1
Address
D4
A4
0
1
0
Slave
1
1
D3
1
A3
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1
0
0
A
C
K
0 0 0 0 0 0 0
Address 1
1
D2
A2
Word
0
receipt of each address byte, the X1227 responds with
an acknowledge. After receiving both address bytes
the X1227 awaits the eight bits of data. After receiving
the 8 data bits, the X1227 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1227 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 11.
1
A1
D1
Address
0
A
C
K
40
Address 0
R/W
Word
A0
A8
D0
Slave Address Byte
Byte 0
Word Address 1
Byte 1
Word Address 0
Byte 2
Data Byte
Byte 3
Characteristics subject to change without notice.
A
C
K
23 Bytes
Data
Address
A
C
K
63
S
o
p
t
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