ADE7758 Analog Devices, ADE7758 Datasheet - Page 37

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

When overflow occurs, the VAR-hr accumulation registers
content can rollover to full-scale negative (0x8000) and continue
increasing in value when the reactive power is positive. Con-
versely, if the reactive power is negative the VAR-hr accumulation
registers content can roll over to full-scale positive (0x7FFF)
and continue decreasing in value.
By setting the REHF bit (Bit 1) of the mask register, the
ADE7758 can be configured to issue an interrupt ( IRQ ) when
Bit 14 of any one of the three VAR-hr accumulation registers
has changed, indicating that the accumulation register is half
full (positive or negative).
Setting the RSTREAD bit (Bit 6) of the LCYMODE register
enables a read-with-reset for the VAR-hr accumulation
registers, i.e., the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation
register is 0.4 µs (4/CLKIN). With full-scale sinusoidal signals
on the analog inputs, and a 90° phase difference between the
voltage and the current signal (the largest possible reactive
power), and the VAR gain registers set to 0x000, the average
word value from each LPF2 is 0xCCCCD. The maximum value
that can be stored in the reactive energy register before it
overflows is 2
added to the internal register, which can store 2
FFFF, FFFF before it overflows, the integration time under these
conditions with VARDIV = 0 is calculated as
When VARDIV is set to a value different from 0, the time
before overflow are scaled accordingly as shown in Equation 21.
Time
Time
=
=
V
I
0xFF,
Time
15
0xD7AE14
0x2851EC
0xD7AE
− 1 or 0x7FFF. As the average word value is first
0xCCCCD
0x2852
CURRENT SIGNAL–i(t)
VOLTAGE SIGNAL–v(t)
0x00
0x00
FFFF,
(
VARDIV
HPF
FFFF
=
SHIFTING FILTER
×
0
90
)
0.4
°
×
PHASE
π
2
μs
VARDIV
=
0.5243
MULTIPLIER
second
40
Figure 72. ADE7758 Reactive Energy Accumulation
SIGN 2
− 1 or 0xFF,
LPF2
6
VAROS[11:0]
(21)
+
Rev. A | Page 37 of 68
2
0
+
2
VARG[11:0]
–1
2
–2
VARDIV[7:0]
2
–3
Energy Accumulation Mode
The reactive power accumulated in each VAR-hr accumulation
register (AVARHR, BVARHR, or CVARHR) depends on the
configuration of the CONSEL bits in the COMPMODE register
(Bit 0 and Bit 1). The different configurations are described in
Table 9.
Table 9. Inputs to VAR-Hr Accumulation Registers
CONSEL[1, 0]
00
01
10
11
Note that IA’/IB’/IC’ are the current phase shifted current waveform.
The contents of the VAR-hr accumulation registers are affected
by both the current gain register (IGAIN) and the VAR gain
register of the corresponding phase.
Reactive Power Frequency Output
Pin 17 (VARCF) of the ADE7758 provides frequency output for
the total reactive power. Similar to APCF, this pin provides an
output frequency that is directly proportional to the total reactive
power. The pulse width of VARPCF is 64 × CLKIN if VARCFNUM
and VARCFDEN are both equal. If VARCFDEN is greater than
VARCFNUM, the pulse width depends on VARCFDEN. The
pulse width in this case is T × (VARCFDEN/2), where T is the
period of the VARCF pulse and VARCFDEN/2 is rounded to
the nearest whole number. An exception to this is when the
period is greater than 180 ms. In this case, the pulse width is
fixed at 90 ms.
A digital-to-frequency converter (DFC) is used to generate the
VARCF pulse output from the total reactive power. The TERMSEL
bits (Bit 2 to Bit 4) of the COMPMODE register can be used to
select which phases to be included in the total reactive power
calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to
the AVARHR, BVARHR, and CVARHR registers in the total
active power calculation. The total reactive power is signed
addition. However, setting the SAVAR bit (Bit 6) in the
COMPMODE register enables absolute value calculation.
%
2
–4
+
+
40
15
VARHR[15:0]
TOTAL REACTIVE POWER IS
ACCUMULATED (INTEGRATED) IN
THE VAR-HR ACCUMULATION REGISTERS
AVARHR
VA × IA’
VA(IA’ – IB’)
VA(IA’ – IB’)
Reserved
0
BVARHR
VB × IB
0
0
Reserved
0
ADE7758
CVARHR
VC × IC’
VC (IC’ – IB’)
VC × IC’
Reserved