MC6800 Motorola, MC6800 Datasheet - Page 15

• Manufacturer Part Number: MC6800
• Description: 8-BIT MICROPROCESSING UNIT (MPU)
• Manufacturer: Motorola

categories: (1) Index Register/ Stack Pointer instructions;
Jump and Branch operations.
Index Register/ Stack Pointer Operations
Decrement (DEX, DES), increment
both. The Compare instruction,
pare the Index Register to a 16-bit value and update the Con-
dition Code Register accordingly.
ed with
“stack. ” The TXS instruction
value equal to one less than the current contents of the Index
“stack”
system.
stored in the MPU’S read/write
contains a 16-bit memory address that is used to access the
list from one end on a last-in-first-out
to the random access mode used by the MPU’S other ad-
extensive use of the stack concept for efficient handling of
Register and Stack Pointer are summarized
LDS), and store (STX, STS) instructions
Register. This causes the next byte to be pulled from the
by describing
dressing modes.
data movement, subroutines and interrupts. The instructi~.os
can be used to establish one or more “stacks”
read/write
amount of memory that is made available.
structions
struction
cumulator
automatically
operation and is “pointing”
The Pull instruction
stacked to be loaded intothe:w’ropriate
Register. The utility of these two instructions can be clarified
location indicated by the Stack Point@r. ~Q&Stack Pointer is
@
@
@
The instructions
The TSX instruction
Program Control
The “stack”
The MC~
Operation of the Stack Pointer with the Pus@,@i~~,Rtill i n-
PO 1NT$&Q$~&&?10
o~eq~,:~$ndex
Store
Store Stack
Stack
Co mp%~$~:her
Oe~.~efit
lnc;&ment
Increment
Load Index
Load Stack
Indx
(Bit
(Bit
(Bit
Reg +Stack
Index
Pntr * Indx
to come from the location indicated by the index
N)
V)
N)
the address of the last data byte put onto the
Index
Stack
(PS HA) causes the contents of kd$~~icated
Stack
Pntr
Pntr
Reg
is illustrated
(A in this example) to be stor~+in;wemory
Reg
.t
Test:
Test:
Test:
memory.
‘*:Z
Reg
Pntr
?::r~ ~~,,,t>~i
Reg
Pntr
Reg
decremented
Pntr
the “stack”
can be thought of as a sequential list of data
Reg
?..*
instruction
!*,.
Sign
2s
!$s.
Result
NS
*,
for direct operation on the MPU’S Index
.s. .
complement
operation
,
(PULA ..@~:~%’B) causes the last byte
‘:.
bit
@
Stack length
MNEMONIC
causes the Index Register to be load-
Iesstha”
in Figures 15 and 1~~..%~.$ush
of
OEX
CPX
O ES
LOX
STX
TXS
TSX
LOS
STS
INX
INS
most
set and interrupt structure allow
to th~~:~e{$empty stack location.
concept
by ~~~~$~t~wing
loads the Stack Pointer with a
can be subdivided
zero?
o“erfiow
significant
memory. The Stack Pointer
MOTOROLA
CPX, can be used to com-
8C
OP
CE
8E
iMMED
(INX, INS), load (LDX,
is limited
-
(LIFO) basis in contrast
3
(Bit
3
3
relative to the M@W
from
=
3
3
3
15=
(MS)
accumulator.
are provided for
9C
OE
9E
DF
OP
9F
PROGRAM CONTROL OPERATIONS
DIRECT
subtraction
1)
byte
-
only <,q~$~~e
4
4
4
5
5
anywhg~~~<
in Table 3.
the storage
.,is,~ ,.,
~
2
2
into two
2
2
2
of
—
AC
AE
AF
OP
EE
EF
at the
result=
The
of
ac-
1
(2)
in-
62
62
62
72
72
m.
1?
byte.?
,,\.
Semiconductor
15
*,..~,@tack Pointer itself) to be stacked as shown in Figure 23.
,.,,,:f?
OP
Bc
FE
BE
FF
BF
“$k MPU status is restored by the Return from Interrupt, RTI, as
f
-$ ‘~~@J& all cause the M PU’S internal registers (except for the
(TNO
5
5
6
6
to the data transfer so that it will point to the last byte stack-
ed rather than the next empty location. Note that the PULL
example, 1A is still in location (m+ 1) following execution of
saved on the stack as shown in Figures
stack is decremented after each byte of,.#$r@?n
pushed onto the stack. For both of$&~~N@structions,
return address is the memory locatid~ f~jo’wing the bytes of
code that correspond to the B,S$.:an’~:$&SRinstruction.
code required for BSR or J
and$%ait
~?~,ah~e
Stack Pointer is automatically
instruction does not “remove”
PULA. A subsequent PUSH instruction would overw~jt~~at
location with the new “pushed”
Subroutine
bytes, depending on whet~r,%~.J
bytes)
Before it is stacked, t@<&~$Yam Counter is automatically
cremented the correct Rgmber of times to be pointing at the
location of the ~$~~~$truction.
lnstruction,,,@K$~~puses
and Ioade@ I$to t~e Program Counter as shown in Figure 21.
M PU.,$0b$wved
shown in Figure 22.
Jump and Branch Operation
Table 4. These instructions are used to control the transferor
operation from one point to another in the control program.
is a jump operation in a very limited sense. Its only effect is to
increment the Program Counter by one. It is useful during
program
struction that is to be determined during debug. It is also us-
ed for equalizing the execution time through alternate paths
in a control program.
There $r~s~$eral
Execution of the Branch to Subroutine (B SR)a$d. #~rrfp to
The Jump and Branch instructions
The No Operation instruction,
—
OP
—
09
08
—
34
31
35
30
IMPLIEO
or
—
—
—
development
4
4
4
4
4
4
(~Q)
for Interrupt
the extende~$~$~$@ bytes) addressing
(JSR) instructions
~
L
1
1
1
1
1
1
I
I
and non-maskable
BOOLEAN/ARITHMETIC
on the stack. The Software Interrupt (SWI)
Products Inc. —
operations that cause the status of the
X–l+x
SP–1-SP
X+l+x
SP+l+SP
MA
M+
XH+M,
SPH+M,
X-1-SP
SP+l+X
as a “stand-in”
(WAI) instructions
XH,
SPH,
the return address to be retrieved
g~g”~<y
(M+l)
XL+(M+l)
(M+1)4SPL
SPL~(M+l)
incremented
the data from memory; in the
cause a returD%~*~
The Return from Subroutine
data.
NOP, while included here,
-XL
S R is in the indexed (two
OPERATION
(N MI) hardware
be either two or three
are summarized
18$~w~@
for some other in-
by one just prior
as well as the
CO ND. COOEREG
i:~).:~ ~.f.,k\,
address is
‘..$.,,,.$,.
20. The
mode.
to be
inter-
*,.,,.:
The
the
in-
in
I