PALCE16V8H-10JC Advanced Micro Devices, PALCE16V8H-10JC Datasheet - Page 5

• Manufacturer Part Number: PALCE16V8H-10JC
• Description: EE CMOS 20-Pin Universal Programmable Array Logic
• Manufacturer: Advanced Micro Devices

Configuration Options
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O, or dedicated input. In the registered output
configuration, the output buffer is enabled by the OE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MC
as a dedicated input derives the input signal from an ad-
jacent I/O. MC
MC
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL0
through SL1
be allowed. SG1 determines whether the PALCE16V8
will emulate a PAL16R8 family or a PAL10H8 family de-
vice. Within each macrocell, SL0
SG1, selects the configuration of the macrocell, and
SL1
for the individual macrocell.
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0
MC
tiplexer. This accommodates CLK being the adjacent
pin for MC
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1
loaded on the LOW-to-HIGH transition of CLK. The
feedback path is from Q on the register. The output
buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Dedicated Output in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
0. All eight product terms are available to the OR gate.
Although the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 15 and 16. Pins
15 and 16 do not use feedback in this mode. Because
CLK and OE are not used in a non-registered device,
pins 1 and 11 are available as input signals. Pin 1 will
2-40
7
0
x
x
AMD
and MC
from pin 1 (CLK).
sets the output as either active low or active high
are the control signals for all four multiplexers. In
7
and OE the adjacent pin for MC
7
7
). SG0 determines whether registers will
, SG0 replaces SG1 on the feedback mul-
0
derives its input from pin 11 (OE) and
0
and MC
7
, a macrocell configured
0
through SL0
x
, in conjunction with
x
.
The flip-flop is
7
0
.
and SL1
PALCE16V8 Family
x
x
=
=
0
use the feedback path of MC
feedback path of MC
Combinatorial I/O in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
1. Only seven product terms are available to the OR
gate. The eighth product term is used to enable the out-
put buffer. The signal at the I/O pin is fed back to the
AND array via the feedback multiplexer. This allows the
pin to be used as an input.
Because CLK and OE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC
feedback path of MC
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
1. Only seven product terms are available to the OR
gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding I/O
signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
1. The output buffer is disabled. Except for MC
the feedback signal is an adjacent I/O. For MC
the feedback signals are pins 1 and 11. These configu-
rations are summarized in Table 1 and illustrated in
Figure 2.
Programmable Output Polarity
The polarity of each macrocell can be active-high or ac-
tive-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is through a programmable bit SL1
controls an exclusive-OR gate at the output of the AND/
OR logic. The output is active high if SL1
low if SL1
SG0 SG1 SL0
0
0
1
1
1
1
1
0
0
1
Table 1. Macrocell Configuration
x
is 0.
0
1
0
1
1
Device Uses No Registers
X
Device Uses Registers
Cell Configuration Devices Emulated
Registered Output
Combinatorial I/O
Combinatorial
Output
Input
Combinatorial I/O
0
0
.
.
7
7
and pin 11 will use the
and pin 11 will use the
PAL16R8, 16R6,
16R4
PAL16R6, 16R4
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
PAL16L8
x
is 1 and active
0
0
and MC
and MC
x
which
x
x
x
=
=
=
7
7