PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet
PCF8523
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PCF8523 Summary of contents
Page 1
... Alarm and timer functions are available with the possibility to generate a wake-up signal on an interrupt pin. An offset register allows fine-tuning of the clock. The PCF8523 has a backup battery switch-over circuit, which detects power failures and automatically switches to the battery supply when a power failure occurs. ...
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... HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 4 4 0.85 mm PCF8523U bare die; 12 bumps (6-6) Figure 41 on page Figure 42 on page 57). Marking codes All information provided in this document is subject to legal disclaimers. ...
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... V BAT SWITCH-OVER CIRCUTRY V SS POWER-ON RESET 2 I C-BUS SDA INTERFACE SCL Fig 1. Block diagram of PCF8523 PCF8523 Product data sheet DIVIDER CLOCK CALIBRATION OFFSET SYSTEM CONTROL REAL-TIME CLOCK ALARM TIMER PCF8523 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 ...
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... OSCO 2 n.c. 3 PCF8523TS 4 V BAT n.c. 6 INT2 7 Top view. For mechanical details, see Pin configuration for TSSOP14 (PCF8523TS) terminal 1 index area OSCI 1 OSCO 2 PCF8523TK V 3 BAT Transparent top view For mechanical details, see Figure 38 on page Pin configuration for HVSON8 (PCF8523TK) All information provided in this document is subject to legal disclaimers. Rev. 3 — ...
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... The substrate (rear side of the die) is connected to V PCF8523 Product data sheet OSCI 2 OSCO 3 PCF8523U V BAT n.c. 6 INT2 7 Viewed from active side. For mechanical details, see Pin configuration for PCF8523U HVSON8 PCF8523U (PCF8523TK [ and [3] [ ...
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... Therefore, faulty reading of the clock and calendar during a carry condition is prevented. The PCF8523 has a battery backup input pin and battery switch-over circuit, which monitors the main power supply and automatically switches to the backup battery when a power failure condition is detected. Accurate timekeeping is maintained even when the main power supply is interrupted ...
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... NXP Semiconductors 8.1 Register overview The 20 registers of the PCF8523 are auto-incrementing after each read or write data byte up to register 13h. After register 13h, the auto-incrementing will wrap around to address 00h (see Fig 6. Table 4. Registers overview Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. ...
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... Section Section PCF8523 1 0 TBC 8.8) 8.3). Bit SR will © NXP B.V. 2011. All rights reserved ...
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... CTBIE 0 1 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Description no watchdog timer A interrupt generated flag set when watchdog timer A interrupt generated; flag is read-only and cleared by reading register Control_2 no countdown timer A interrupt generated flag set when countdown timer A interrupt generated ...
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... BLIE 0 1 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Description [1] battery switch-over and battery low detection control unused no battery switch-over interrupt generated flag set when battery switch-over occurs; flag ...
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... PCF8523 P/S 013aaa320 © ...
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... The flag BLF is read only cleared automatically from the battery low detection circuit when the battery is replaced. PCF8523 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar © NXP B.V. 2011. All rights reserved ...
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... BSF BSF: BATTERY FLAG SET CLEAR to interface: read BLF BLF: BATTERY LOW FLAG SET CLEAR All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar SIE 0 1 TAM INT1 INT1/CLKOUT TAM CLKOUT CTAIE 0 1 ...
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... PCF8523 automatically enters the standby mode. In standby mode the DD PCF8523 will not draw any power from the backup battery until the device is powered up from the main power supply V mode whenever the main power supply also possible to enter into standby mode when the chip is already supplied by main power supply V power management control bits PM[2:0] have to be set logic 111 ...
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... NXP Semiconductors 8.5.2 Battery switch-over function The PCF8523 has a backup battery switch-over circuit, which monitors the main power supply V condition is detected. One of two operation modes can be selected: • Standard mode: the power failure condition happens when • Direct switching mode: the power failure condition happens when V ...
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... Battery switch-over behavior in standard mode and with bit BSIE set logic 1 (enabled) All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 Real-Time Clock (RTC) and calendar . DD . BAT internal power supply (= V ) BBS PCF8523 V BBS cleared via interface 013aaa321 © NXP B.V. 2011. All rights reserved ...
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... The V • The battery flag (BSF) is always logic 0. 8.5.3 Battery low detection function The PCF8523 has a battery low detection circuit, which monitors the status of the battery V . BAT Generation of interrupts from the battery low detection is controlled via bit BLIE (register Control_3). If BLIE is enabled the INT1 will follow the status of bit BLF (register Control_3) ...
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... BAT BBS BAT BLF All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 Real-Time Clock (RTC) and calendar , the following sequence occurs (see th(bat)low internal power supply (= V ) BBS V BAT PCF8523 013aaa323 © NXP B.V. 2011. All rights reserved ...
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... BCD format unit place Digit (unit place) Bit Figure 12). The flag will remain PCF8523 © NXP B.V. 2011. All rights reserved ...
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... Register Days Table 14. Bit [1] The PCF8523 compensates for leap years by adding a 29 value, which is exactly divisible by 4, including the year 00. PCF8523 Product data sheet and flag can not be cleared DD Minutes - minutes register (address 04h) bit description ...
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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Description unused actual weekday, values see Table ...
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... Real-Time Clock (RTC) and calendar Place value Description ten’s place actual year coded in BCD format unit place 1 Hz tick SECONDS MINUTES HOURS DAYS WEEKDAYS MONTHS YEARS 013aaa324 14). t < DATA DATA STOP PCF8523 013aaa215 © NXP B.V. 2011. All rights reserved ...
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... HOURS All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Place value Description - minute alarm is enabled - minute alarm is disabled ten’s place minute alarm information coded in ...
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... WEEKDAY ALARM = WEEKDAY TIME It’s only on increment to a matched case that the alarm flag is set, see All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Place value Description - day alarm is enabled - day alarm is disabled ...
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... AF. In this example, bit CTAF, Example to clear only AF (bit 3) Bit All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar 8. 001aaf903 ...
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... Example where only the minute alarm is used and no other interrupts are enabled. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 Real-Time Clock (RTC) and calendar CLEAR INSTRUCTION 013aaa335 PCF8523 © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 8.8 Register Offset The PCF8523 incorporates an offset register (address 0Eh), which can be used to implement several functions, like: • Aging adjustment, • Temperature compensation, • Accuracy tuning. Table 26. Bit [1] Default value. Each LSB will introduce an offset of 4.34 ppm for MODE = 0 and 4.069 ppm for MODE = 1. The values of 4.34 ppm and 4.069 ppm are based on a nominal 32.768 kHz clock. The offset value is coded in two’ ...
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... Effect of clock correction for MODE = 0 no effect no effect no effect no effect no effect effected effected All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Minute Correction pulses on INT1 per minute and 01 1 00, 01, and 02 ...
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... For multiple pulses they are repeated at an interval of 31). Timer source clock frequency (Hz) 4096 64 1 1 3600 - - PCF8523 [1] Effect of correction no effect effected effected effected effected - - © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 8.9 Timer function The PCF8523 has three timers: • Timer A can be used as a watchdog timer or a countdown timer (see can be configured by using TAC[1:0] in the Tmr_CLKOUT_ctrl register (0Fh). • Timer B can be used as a countdown timer (see by using TBC in the Tmr_CLKOUT_ctrl register (0Fh). ...
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... CLKOUT = high CLKOUT = high-Z [ CLKOUT = high-Z [ CLKOUT = high-Z Description unused source clock for timer A (see 4.096 kHz 3600 PCF8523 Table 38) © NXP B.V. 2011. All rights reserved ...
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... Tmr_B_reg - timer B value register (address 13h) bit description Symbol Value TIMER_B_VALUE[7: All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Description timer-period in seconds n timerperiod = ---------------------------------------------------------- - sourceclockfrequency where n is the countdown value ...
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... Hz 15.625 3600 Figure All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Units Maximum timer-period (n = 255) s 62.256 ms 3.984 s 255 min 255 hour 255 ...
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... The next timer-period starts. PCF8523 Product data sheet INT1 TAC[1:0] = 10, WTAIE = 1, WTAF = 1, an interrupt is generated. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar MCU n 013aaa327 © NXP B.V. 2011. All rights reserved ...
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... Maximum timer-period PCF8523 013aaa328 © NXP B.V. 2011. All rights reserved ...
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... In this example assumed that the countdown timer flag (CTBF) is cleared before the next countdown period expires and that interrupt output is set to pulse mode. Section 8.7.5. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Figure 20 ...
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... Tmr_CLKOUT_ctrl) is used to control this mode selection. Interrupt output may be disabled with the CTBIE bit (register Control_2). 8.9.4 Second interrupt timer PCF8523 has a pre-defined timer, which is used to generate an interrupt once per second. The pulse generator for the second interrupt timer operates from an internal 64 Hz clock and generates a pulse of timer and can be switched on and off by the SIE bit in register Control_1 (00h) ...
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... In this example, bit TAM is set logic 0 and the SF flag is cleared after an interrupt. Interrupt low pulse width for timer A Interrupt pulse width [ 122 s 7.812 ms 15.625 ms 15.625 ms 15.625 ms All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar ...
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... The timing shown for clearing bit SF is also valid for the non-pulsed interrupt mode, i.e. when TAM set logic 0, where the INT1 pulse may be shortened by setting SIE logic 0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar [1] n > 1 244 ...
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... The timing shown for clearing CTAF is also valid for the non-pulsed interrupt mode, i.e. when TAM set logic 0, where the INT1 pulse may be shortened by setting CTAIE logic 0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar CLEAR INSTRUCTION 013aaa334 © ...
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... RES 512 Hz CLKOUT source 8192 Hz 16384 Hz and F ) are not reset and because the Figure 26). 0 μs to 122 μs and PCF8523 tick RES stop 013aaa336 2 C-bus 001aaf912 not being reset (see © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Comment prescaler counting normally prescaler is reset; time circuits are frozen prescaler is reset; time circuits are frozen prescaler is now running - - - : - transition of F14 increments the time circuits ...
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... SCL data line stable; data valid Figure 28). S START condition All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar 27). change of data allowed mbc621 P STOP condition © NXP B.V. 2011. All rights reserved. SDA ...
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... SCL MASTER TRANSMITTER RECEIVER Fig 29. System configuration The PCF8523 can act as a slave transmitter and a slave receiver. 8.11.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. ...
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... Table 44. Bit After a start condition, a valid hardware address has to be sent to a PCF8523 device. The R/W bit defines the direction of the following single or multiple byte data transfer. For the format and the timing of the START condition (S), the STOP condition (P) and the ...
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... NXP Semiconductors 9. Internal circuitry Fig 33. Device diode protection diagram of PCF8523 PCF8523 Product data sheet PCF8523 OSCI OSCO V BAT V SS INT2 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar V DD INT1/CLKOUT SCL ...
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... Ref. 8 “JESD78” All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Conditions Min 0.5 50 0.5 0.5 10 ...
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... T amb active 3 BAT All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar pF; unless otherwise s L Min Typ Max [1] 1.2 - 5.5 [2] 1.0 - 5.5 1 ...
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... L Min Typ 0 [6] 1 [7][8] 3 12.5 [ OSCI OSCO C = ------------------------------------------- - in series: L itg OSCI OSCO PCF8523 Max Unit 5 100 k . © NXP B.V. 2011. All rights reserved ...
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... Max [2] - 100 4 250 - - 4.7 - [3][4] - 1000 [3][4] - 300 - 400 [5] - 3.45 [6] - 3.45 [ < 5 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Min Max Min Max - 400 - 1000 1.3 - 0.5 - 0.6 - 0.26 - 100 - 1.3 - 0.5 - 0.6 - 0.26 - 0.6 - 0.26 - 0 0.1C 300 - 120 0.1C 300 - 120 ...
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... VD;DAT VD;ACK SU;STO 013aaa417 SCL MASTER TRANSMITTER RECEIVER SDA SCL pull-up resistor drops to fast, the internal supply switch PCF8523 013aaa341 © NXP B.V. 2011. All rights reserved ...
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... Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION IEC SOT96-1 076E03 Fig 36. Package outline SOT96-1 (SO8) of PCF8523T PCF8523 Product data sheet ...
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... Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT402-1 Fig 37. Package outline SOT402-1 (TSSOP14) of PCF8523TS PCF8523 Product data sheet 2.5 ...
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... DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0 0.2 0.00 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION IEC SOT909-1 Fig 38. Package outline SOT909-1 (HVSON8) of PCF8523TK PCF8523 Product data sheet (1) (1) ...
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... NXP Semiconductors 15. Bare die outline Bare die; 12 bumps (6- European projection Fig 39. Bare die outline of PCF8523U (for dimensions see Table 48. Original dimensions are in mm. Unit (mm) max nom min [1] Dimension includes saw lane. [2] P and P 1 [3] P and P 2 PCF8523 ...
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... Alignment mark dimension and location [1] [2] Figure 40). REF y x All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Coordinates ( 714.4 911.7 714.4 988.3 714.4 707.3 714.4 199.3 714.4 ...
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... Die marking code. Seal ring plus gap to active circuit ~18 m. Wafer thickness 200 m. PCF8523U: bad die are marked in wafer mapping. Fig 41. PCF8523U wafer information plastic frame ∅ 250 mm 276 mm Fig 42. Film Frame Carrier (FFC) (for PCF8523U) ...
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... Solder bath specifications, including temperature and impurities PCF8523 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar © NXP B.V. 2011. All rights reserved ...
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... Package reflow temperature (C) 3 Volume (mm ) < 350 260 260 250 Figure 43. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Figure 43) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar peak temperature time 001aac844 © NXP B.V. 2011. All rights reserved. ...
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... Parts Per Million Real-Time Clock Serial CLock line Serial DAta line Surface Mount Device Slew Rate All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar © NXP B.V. 2011. All rights reserved ...
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... SNV-FA-01-02 — Marking Formats Integrated Circuits [12] UM10204 — I PCF8523 Product data sheet 2 C-bus specification and user manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar © NXP B.V. 2011. All rights reserved ...
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... Product data sheet Table 46 Product data sheet Table 46 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar Change notice Supersedes - PCF8523 v.2 - PCF8523 v.1 Table © NXP B.V. 2011. All rights reserved ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar © NXP B.V. 2011. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 March 2011 PCF8523 Real-Time Clock (RTC) and calendar © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8523 All rights reserved. Date of release: 30 March 2011 Document identifier: PCF8523 ...