PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 36

• Manufacturer Part Number: PCF8523
• Description: Real-Time Clock (RTC) and calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8523
Product data sheet
8.9.3 Timer B
When the interrupt generation is enabled (CTAIE = 1) and the countdown timer flag CTAF
is set logic 1, an interrupt signal on INT1 will be generated. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal,
which follows the condition of CTAF (register Control_2). The TAM bit (register
Tmr_CLKOUT_ctrl) is used to control this mode selection. The interrupt output may be
disabled with the CTAIE bit (register Control_2).
Timer B can only be used as a countdown timer and can be switched on and off by the
TBC bit in register Tmr_CLKOUT_ctrl (0Fh).
The generation of interrupts from the countdown timer is controlled via the CTBIE bit
(register Control_2).
When enabled, it counts down from the software programmed 8 bit binary value n in
register Tmr_B_reg (13h). When the counter reaches 1, on the next rising edge of the
timer clock the following events occur (see
At the end of every countdown, the timer sets the countdown timer flag CTBF (register
Control_2). CTBF may only be cleared by using the interface. Instructions, how to clear a
flag, is given in
When reading the timer, the current countdown value is returned and not the initial
value n. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
Fig 20. General countdown timer behavior
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countdown value, n
countdown counter
The countdown timer flag CTBF (register Control_2) is set logic 1.
When the interrupt generation is enabled (CTBIE = 1), interrupt signals on INT1 and
INT2 will be generated.
The counter automatically reloads.
The next timer-period starts.
timer source clock
WD/CD [1:0]
INT1/INT2
In this example, it is assumed that the countdown timer flag (CTBF) is cleared before the next
countdown period expires and that interrupt output is set to pulse mode.
CTBF
Section
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Rev. 3 — 30 March 2011
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8.7.5.
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Figure
duration of first timer period after
enable may range from n−1 to n+1
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20):
Real-Time Clock (RTC) and calendar
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PCF8523
© NXP B.V. 2011. All rights reserved.
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