PCF8563BS NXP [NXP Semiconductors], PCF8563BS Datasheet

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PCF8563 Real-time clock/calendar Rev. 06 — 21 February 2008 1. General description The PCF8563 is a CMOS real-time clock/calendar optimized for low power consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All addresses and data ...

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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Topside Package mark Name PCF8563P PCF8563P DIP8 PCF8563T 8563T SO8 PCF8563TS 8563 TSSOP8 PCF8563BS 8563S HVSON10 5. Block diagram OSCI OSCILLATOR 32.768 kHz OSCO MONITOR POWER ON RESET WATCH DOG 2 SDA I C-BUS ...

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... Rev. 06 — 21 February 2008 PCF8563 Real-time clock/calendar 1 OSCI 2 OSCO PCF8563T INT 001aaf975 Fig 3. Pin configuration SO8 terminal 1 index area OSCI 1 OSCO 2 PCF8563BS n.c. 3 INT Transparent top view Fig 5. Pin configuration HVSON10 CLKOUT 6 SCL 5 SDA PCF8563 mgr886 ...

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NXP Semiconductors 6.2 Pin description Table 2. Symbol OSCI OSCO n.c. INT V SS SDA SCL CLKOUT V DD n.c. 7. Functional description The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with ...

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NXP Semiconductors 7.2 Timer The 8-bit countdown timer at address 0Fh is controlled by the timer control register at address 0Eh. The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 ...

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NXP Semiconductors 7.6 Register organization Table 3. Formatted registers overview Bit positions labelled as x are not relevant. Bit positions labelled with 0 should always be written with logic 0; if read they could be either logic 0 or logic ...

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NXP Semiconductors Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set. ...

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NXP Semiconductors Table 8. Bit Table 9. Bit Table 10. Bit [1] The PCF8563 compensates for leap years by adding a 29th day to ...

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NXP Semiconductors Table 14. Month January February March April May June July August September October November December Table 15. Bit 7.6.4 Alarm registers When one or more of these registers are loaded with a valid minute, hour, ...

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NXP Semiconductors Table 18. Bit Table 19. Bit 7.6.5 Clock output control register Table 20. Bit Table 21. FD1 0 0 ...

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NXP Semiconductors Table 22. Bit Table 23. TD1 Table 24. Bit 7.7 EXT_CLK test mode A Test mode is available which allows for on-board testing. In ...

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NXP Semiconductors Operation example: 1. Set EXT_CLK test mode (control_status_1, bit TEST1 = 1) 2. Set STOP (control_status_1, bit STOP = 1) 3. Clear STOP (control_status_1, bit STOP = 0) 4. Set time registers to desired value 5. Apply 32 ...

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NXP Semiconductors Table 25. Address Register name 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh [1] registers marked ‘x’ are undefined at power-up and unchanged by subsequent resets. 8. Characteristics of the I 2 The I C-bus ...

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NXP Semiconductors SDA SCL Fig 10. Definition of start and stop conditions 8.3 System configuration A device generating a message is a transmitter, a device receiving a message is a receiver. The device that controls the message is the master ...

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NXP Semiconductors by transmitter Fig 12. Acknowledgement on the I 2 8.5 I C-bus protocol 8.5.1 Addressing Before any data is transmitted on the I addressed first. The addressing is always carried out with the first byte transmitted after the ...

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NXP Semiconductors S SLAVE ADDRESS Fig 14. Master transmits to slave receiver (Write mode) acknowledgement from slave S SLAVE ADDRESS 0 A R/W Fig 15. Master reads after setting word address (write word address; read data) S SLAVE ADDRESS Fig ...

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NXP Semiconductors 9. Limiting values Table 26. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I supply current DD V input voltage I V output voltage O I input current ...

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NXP Semiconductors Table 27. Static characteristics specified. Symbol Parameter I supply current DD Inputs V LOW-level input IL voltage V HIGH-level input IH voltage I input ...

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NXP Semiconductors 0.8 0.6 0.4 0 Timer = 1 minute. amb Fig 17. Supply current function of supply DD voltage V ; CLKOUT disabled DD ...

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NXP Semiconductors 11. Dynamic characteristics Table 28. Dynamic characteristics specified. Symbol Parameter Oscillator C integrated load capacitance L(itg relative oscillator frequency variation osc osc ...

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NXP Semiconductors SDA SCL SDA Fig 21. I 12. Application information Fig 22. Application diagram PCF8563_6 Product data sheet t t BUF LOW t HD;STA C-bus timing waveforms SCL CLOCK CALENDAR OSCI PCF8563 ...

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NXP Semiconductors 12.1 Quartz frequency adjustment 12.1.1 Method 1: fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after ...

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NXP Semiconductors 13. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. ...

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NXP Semiconductors SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 ...

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NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 ...

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NXP Semiconductors HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the ...

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NXP Semiconductors 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5 . 15. Soldering of SMD ...

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NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities ...

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NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . PCF8563_6 Product data sheet maximum peak temperature = MSL limit, damage level ...

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NXP Semiconductors 16. Revision history Table 31. Revision history Document ID Release date PCF8563_6 20080221 • Modifications: Register names modified in • Figure PCF8563_5 20070717 • Modifications: The format of this data sheet has been redesigned to comply with the ...

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NXP Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...