PCF8563BS NXP [NXP Semiconductors], PCF8563BS Datasheet - Page 13

• Manufacturer Part Number: PCF8563BS
• Description: Real-time clock/calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
8. Characteristics of the I
PCF8563_6
Product data sheet
8.1 Bit transfer
8.2 Start and stop conditions
Table 25.
[1]
The I
The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P); see
Address Register name
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Fig 9.
registers marked ‘x’ are undefined at power-up and unchanged by subsequent resets.
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
Bit transfer
days
weekdays
century_months
years
minute_alarm
hour_alarm
day_alarm
weekday_alarm
CLKOUT_control
timer_control
timer
Register reset value
2
SDA
SCL
Figure
C-bus
Rev. 06 — 21 February 2008
10.
Bit 7
x
x
x
x
1
1
1
1
1
0
x
[1]
…continued
data valid
data line
stable;
Bit 6
x
x
x
x
x
x
x
x
x
x
x
Figure
Bit 5
x
x
x
x
x
x
x
x
x
x
x
allowed
change
of data
9).
Bit 4
x
x
x
x
x
x
x
x
x
x
x
Bit 3
x
x
x
x
x
x
x
x
x
x
x
Real-time clock/calendar
mbc621
Bit 2
x
x
x
x
x
x
x
x
x
x
x
PCF8563
© NXP B.V. 2008. All rights reserved.
Bit 1
x
x
x
x
x
x
x
x
0
1
x
Bit 0
x
x
x
x
x
x
x
x
0
1
x
13 of 32