PCA85232DA NXP [NXP Semiconductors], PCA85232DA Datasheet
PCA85232DA
Related parts for PCA85232DA
PCA85232DA Summary of contents
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PCA85232 LCD driver for low multiplex rates Rev. 1 — 8 December 2010 1. General description The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and up ...
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NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name PCA85232U/2DA/Q1 bare die 4. Marking Table 2. Type number PCA85232U/2DA/Q1 PCA85232 Product data sheet Description 197 bumps; 6.5 × 1.16 × 0.40 mm Marking codes All information ...
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NXP Semiconductors 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA85232 PCA85232 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS ...
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Pinning information 6.1 Pinning PCA85232 Viewed from active side. For mechanical details, see Fig 2. Pinning diagram of PCA85232 + Figure 32. 013aaa283 ...
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NXP Semiconductors 6.2 Pin description Table 3. Symbol SDAACK [1] SDA SCL CLK V DD SYNC OSC T1, T2 and T3 A0 and A1 SA0 [ LCD BP2 and BP0 S0 to S79 BP0, BP2, BP1, and ...
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NXP Semiconductors 7. Functional description The PCA85232 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure backplanes and up to 160 segments. The ...
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NXP Semiconductors Fig 4. The host microprocessor or microcontroller maintains the 2-line I channel with the PCA85232. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The ...
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NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. ...
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NXP Semiconductors Using Equation ⁄ 1 bias is 2 ⁄ 1 bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ...
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NXP Semiconductors Fig 5. PCA85232 Product data sheet 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 ...
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NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig 6. ...
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NXP Semiconductors 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85232 allows the use of Figure 8. Fig 7. PCA85232 Product data sheet ⁄ bias or 2 ...
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NXP Semiconductors Fig 8. PCA85232 Product data sheet V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD LCD 2V /3 LCD LCD ...
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NXP Semiconductors 7.4.3 1:3 multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Fig 9. PCA85232 Product data sheet Figure 9. V LCD 2V /3 LCD BP0 V /3 ...
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NXP Semiconductors 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 10. Waveforms for ...
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NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency f which either is derived from the built-in oscillator frequency f clk f = clk or equals an external clock ...
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NXP Semiconductors 7.8 Segment outputs The LCD drive section includes 160 segment outputs (S0 to S159) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data ...
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NXP Semiconductors Fig 11. Display RAM bitmap When display data is transmitted to the PCA85232 the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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NXP Semiconductors 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte series of display data bytes, into any location of the ...
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NXP Semiconductors The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of ...
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NXP Semiconductors By connecting pin SDAACK to pin SDA on the PCA85232, the SDA line becomes fully 2 I C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, ...
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NXP Semiconductors 7.16.2 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are ...
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NXP Semiconductors 2 7.16.4 I C-bus controller The PCA85232 acts transmit data the acknowledge signals from the selected devices. Device selection depends on the 2 I C-bus slave address, on the transferred command data, ...
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NXP Semiconductors R slave address control byte EXAMPLES a) transmit two bytes of RAM data ...
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NXP Semiconductors The acknowledgement after each byte is made only by the (A0 and A1) addressed PCA85232. After the last (display) byte, the I Alternatively a START may be asserted to RESTART an I 7.17 Command decoder The command decoder ...
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NXP Semiconductors Table 12. Bit [1] Power-on and reset value. Table 13. Bit [1] Power-on and reset value. Table 14. Bit [1] The ...
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NXP Semiconductors Table 16. Bit [1] Nominal frame frequency calculated for an internal operating frequency of 3.5 kHz. [2] Power-on and reset value. 7.18 Display controller The display controller executes the commands identified by ...
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NXP Semiconductors 8. Internal circuitry Fig 19. Device protection diagram PCA85232 Product data sheet V LCD S0 to S159, BP0 to BP3 SYNC, T1, T2, A0, A1, OSC, CLK, SA0 V SS All information provided in ...
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NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 17. In accordance with the Absolute Maximum Rating System ...
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NXP Semiconductors 10. Static characteristics Table 18. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I ...
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NXP Semiconductors Table 18. Static characteristics Symbol Parameter LCD outputs ΔV output voltage variation O R output resistance O [1] LCD outputs are open-circuit; inputs at ...
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NXP Semiconductors Fig 21. I PCA85232 Product data sheet 70 I DD(LCD) (μ °C; 1:4 multiplex; all RAM written with logic 1; no display connected amb f = 3.500 kHz. clk(ext) ...
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NXP Semiconductors 11. Dynamic characteristics Table 19. Dynamic characteristics Symbol Parameter f clock frequency clk f external clock frequency clk(ext) t HIGH-level clock time clk(H) t ...
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NXP Semiconductors Fig 22. Typical clock frequency (f (Hz) Fig 23. Frame frequency variation PCA85232 Product data sheet 3540 f clk (Hz) 3500 3460 3420 3380 3340 °C. T amb ) with respect to V clk ...
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NXP Semiconductors BP0 to BP3, and S0 to S159 Fig 24. Driver timing waveforms SDA SCL HD;STA clock cycle ...
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NXP Semiconductors 12. Application information 12.1 Pull-up resistor sizing on I 12.1.1 Max value of pull-up resistor The bus capacitance (C capacitance on pin SDA limits the maximum value of the pull-up resistor (R specified rise time. According to the ...
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NXP Semiconductors R PU(max) (kΩ) Fig 26. Values for R R PU(min) (kΩ) Fig 27. Values for R 12.2 SDA and SDAACK configuration The Serial DAta line (SDA) and the I lines can be connected together to facilitate a single ...
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NXP Semiconductors 12.3 Cascaded operation In large display configurations PCA85232 can be distinguished on the same 2 I C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable 2 I C-bus slave address (SA0). ...
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NXP Semiconductors Table 21. Number of devices the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is connected to V the CLK pin. The other PCA85232 devices are having ...
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NXP Semiconductors V LCD V DD MICRO- PROCESSOR/ MICRO- CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 29. Cascaded configuration with two PCA85232 using the internal clock of the master ...
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NXP Semiconductors V LCD V DD PROCESSOR/ CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 30. Cascaded configuration with one PCA85232 and one PCA85133 using the internal PCA85232 Product data ...
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NXP Semiconductors Fig 31. Synchronization of the cascade for the various PCA85232 drive modes PCA85232 Product data sheet = BP0 SYNC (a) static drive mode BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1:2 multiplex drive mode ...
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NXP Semiconductors 13. Bare die outline Bare die; 197 bumps; 6.5 x 1.16 x 0.40 mm 166 C1 Marking code: PC85132/232-1 167 e Dimensions (1) (1) (1) Unit max 0.018 mm nom 0.40 0.015 ...
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NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol SDAACK SDAACK SDAACK SDA SDA SDA SCL SCL SCL CLK V ...
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NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 ...
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NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 ...
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NXP Semiconductors Fig 33. Alignment marks PCA85232 Product data sheet REF S1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates REF C1 001aah849 © ...
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NXP Semiconductors 14. Packing information Table 25. Symbol Fig 34. Tray details PCA85232 Product data sheet Tray dimensions (see Figure 34) Description pocket pitch in x direction pocket pitch in y direction ...
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NXP Semiconductors Fig 35. Tray alignment 15. Abbreviations Table 26. Acronym AEC COG DC HBM ITO LCD LSB MM MSB POR RC RAM RMS SCL SDA PCA85232 Product data sheet Abbreviations Description Automotive Electronics Council Chip-On-Glass ...
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NXP Semiconductors 16. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10706 — Handling bare die [3] AN10853 — ESD and EMC sensitivity of IC [4] IEC 60134 — Rating systems for electronic ...
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NXP Semiconductors 18. Legal information 18.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die — All die are tested on compliance with ...
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NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...