AD7346B AD [Analog Devices], AD7346B Datasheet - Page 6

• Manufacturer Part Number: AD7346B
• Description: 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
• Manufacturer: AD [Analog Devices]

Mnemonic
POWER SUPPLY
VDRIVE
AGND
AGND
DVDD
D G N D
TRANSMIT CHANNEL
TxDATA
T x S Y N C
TxCLK
T x D E C O U P
DRV-OUTP
DRV-OUTN
EXTERNAL INTERFACE
SPICLK
T F S
D T
D R
R E S E T B
PWRDWNB
FCLK
T E S T
RECEIVE CHANNEL
HYBIN-2B
HYBIN-2A
HYBIN-1B
HYBIN-1A
F I L T O U T P
F I L T O U T N
ADCINP
ADCINN
CAP-T
CAP-B
VREF
R E F - C O M
C O M - L V L
ADCCLK
SCLK
S D O
AD5011
Digital output drive level.
Analog power supply.
Analog Ground.
Positive power supply for the digital section.
Digital Ground.
Transmit data input.
Transmit data frame synchronization, logic input.
Transmit serial clock, logic input.
Transmit DAC reference decoupling pin.
external decoupling.
Differential line driver positive output.
Differential line driver negative output.
Serial interface clock, logic input.
Serial Interface frame synchronisation, logic input.
Serial interface data input.
Serial interface data output.
Master Reset. This is an active low logic input.
Master powerdown.
sleep mode.
Filter tuning clock. The clock for the filter tuning circuit in both the transmit and receive paths is
supplied to FCLK. A 16.384 MHz should be connected to this pin to obtain the specified
frequencies.
Test Mode. When TEST is tied to DVDD, the AD5011 is placed in a test mode. For normal
operation, this pin should be tied to DGND.
Hybrid non-inverting input.
Hybrid inverting input.
Hybrid inverting input.
Hybrid non-inverting input.
Positive differential output of the antialiasing filter.
Negative differential output of the antialiasing filter.
Positive differential input to the ADC.
Negative differential input to the ADC.
Receive ADC reference decoupling pin.
decoupling.
Receive ADC reference decoupling pin.
decoupling.
Voltage Reference.
Reference common.
Common mode level.
ADC Sample clock, logic input.
ADC serial interface clock, logic input.
ADC serial data out.
Function
The external reference is applied to this pin.
When PWRDWNB is taken low, the complete AD5011 device is placed in a
PIN DESCRIPTION
This clock also operates as the frame synchronization.
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The reference which supplies the ADC needs some external
The reference which supplies the ADC needs some external
The reference which supplies the DAC needs some
REV PrA