AD9884A/PCB AD [Analog Devices], AD9884A/PCB Datasheet - Page 11

• Manufacturer Part Number: AD9884A/PCB
• Description: 100 MSPS/140 MSPS Analog Flat Panel Interface
• Manufacturer: AD [Analog Devices]

GENERAL CONTROL
A bit that determines whether all pixels are presented to a single
port (A), or alternating pixels are demultiplexed to Ports A and B.
DEMUX
0
1
When DEMUX = 0, Port B outputs are in a high impedance
state.
The power-up default value is DEMUX = 1.
Setting this bit to a Logic 1 delays data on Port A and the
DATACK output by one-half DATACK period so that the
rising edge of DATACK may be used to externally latch data
from both Port A and Port B. When this bit is set to a Logic 0,
the rising edge of DATACK may be used to externally latch
data from Port A only, and the DATACK rising edge may be
used to externally latch data from Port B.
PARALLEL
0
1
When in single port mode (DEMUX = 0), this bit is ignored.
The power-up default value is PARALLEL = 1.
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the HSYNC input.
HSPOL
0
1
Active LOW is the traditional negative-going HSYNC pulse.
Sampling timing is based on the leading edge of HSYNC, which
is the FALLING edge. The Clamp Position, as determined by
CLPLACE, is measured from the trailing edge.
Active HIGH is inverted from the traditional HSYNC, with a
positive-going pulse. This means that sampling timing will be
based on the leading edge of HSYNC, which is now the RIS-
ING edge, and clamp placement will count from the FALLING
edge.
The device will operate more-or-less properly if this bit is set
incorrectly, but the internally generated clamp position, as es-
tablished by CLPOS, will not be placed as expected, which may
generate clamping errors.
The power-up default value is HSPOL = 1.
A bit that must be set to indicate the polarity of the COAST
signal that is applied to the COAST input.
REV. B
0A
0A
0A
0A
7
6
5
4
Data Alternates Between Ports
Simultaneous Data on Alternate DATACKs
Function
DEMUX
Function
All Data Goes to Port A
Alternate Pixels Go to Port A and Port B
PARALLEL
HSPOL
Function
Active LOW
Active HIGH
CSTPOL
Output Port Select
Output Timing Select
HSYNC Polarity
COAST Polarity
–11–
CSTPOL
0
1
Active LOW means that the clock generator will ignore HSYNC
inputs when COAST is LOW, and continue operating at the
same nominal frequency until COAST goes HIGH.
Active HIGH means that the clock generator will ignore HSYNC
inputs when COAST is HIGH, and continue operating at the
same nominal frequency until COAST goes LOW.
The power-up default value is CSTPOL = 1.
A bit that determines the source of clamp timing.
EXTCLMP
0
1
A 0 enables the clamp timing circuitry controlled by CLPLACE
and CLDUR. The clamp position and duration is counted from
the trailing edge of HSYNC.
A 1 enables the external CLAMP input pin. The three channels
are clamped when the CLAMP signal is active. The polarity of
CLAMP is determined by the CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
A bit that determines the polarity of the externally provided
CLAMP signal.
CLAMPOL
0
1
A 0 means that the circuit will clamp when CLAMP is LOW,
and it will pass the signal to the ADC when CLAMP is HIGH.
A 1 means that the circuit will clamp when CLAMP is HIGH,
and it will pass the signal to the ADC when CLAMP is LOW.
The power-up default value is CLAMPOL = 1.
A bit that determines the source of the pixel clock.
EXTCLK
0
1
A 0 enables the internal PLL that generates the pixel clock from
an externally-provided HSYNC.
A 1 enables the external CKEXT input pin. In this mode, the
PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust
(PHASE) is still functional.
The power-up default value is EXTCLK = 0.
0A
0A
0A
3
2
1
Internally-generated clamp
Externally-provided clamp signal
Active LOW
Active HIGH
Internally generated clock
Externally provided clock signal
Function
Function
Function
Function
Active LOW
Active HIGH
EXTCLMP
CLAMPOL
EXTCLK
Clamp Signal Source
Clamp Signal Polarity
External Clock Select
AD9884A